Write-Per-Bit Cycle (/G = High)
tC
tRE
/RE
0, 2
tRP
tMSU
tMH
/F
tMSU
tMH
W/R
tAC
tASR
tCAH
tRAH
tCAH
Column 2
tACH
tASC
A
Row
Column 1
tASC
tCAH
tASC
tCAE
tCLV
Column 3
0-10
tRSH
t CHR
tCRP
tCAE
tWCH
tCAE
/CAL
tCQH
0-3,P
tCQV
tCWL
tWP
tWRP
tRRH
tCLV
/WE
tWHR
tRAC2
tRWL
tAC
tWQV
tCQX
DQ
Read Data
Write Data
tDH
Read Data
0-35
tWQX
tGQV
tDS
tGQX
tGQZ
tGQZ
tGQV
/G
/S
tSSR
Don’t Care or Indeterminate
NOTES: 1. If column address one equals column address two, then a read-modify-write cycle is performed.
2.
Parity bits DQ
must have mask provided at falling edge of /RE.
8,17,26,35
2-90