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TFP401PZP 参数 Datasheet PDF下载

TFP401PZP图片预览
型号: TFP401PZP
PDF下载: 下载PDF文件 查看货源
内容描述: SLDS120B - 2000年3月 - 修订2003年6月 [SLDS120B - MARCH 2000 – REVISED JUNE 2003]
分类和应用: 商用集成电路PC
文件页数/大小: 19 页 / 341 K
品牌: QUANTUM [ QUANTUM RESEARCH GROUP ]
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TFP401, TFP401A
TI
PanelBus
DIGITAL RECEIVER
SLDS120B - MARCH 2000 – REVISED JUNE 2003
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description
PowerPAD advanced packaging technology results in best of class power dissipation, footprint, and ultra-low
ground inductance.
The TFP401/401A combines
PanelBus
circuit innovation with TI’s advanced 0.18-µm EPIC-5 CMOS
process technology, along with TI PowerPAD package technology to achieve a reliable, low-powered, low
noise, high-speed digital interface solution.
AVAILABLE OPTIONS
PACKAGED DEVICE
100-TQFP
(PZP)
TFP401PZP
TFP401APZP
PanelBus,
PowerPAD and EPIC-5 are trademarks of Texas Instruments.
I2C is a licensed bus protocol from Phillips Semiconductor, Inc.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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The Digital Visual Interface Specification, DVI, is an industry standard developed by the Digital Display Working Group (DDWG) for
high-speed digital connection to digital displays The TFP401 and TFP401A are compliant to the DVI Specification Rev. 1.0.
The TFP401/401A has an internal voltage regulator that provides the 1.8-V core power supply from the externally supplied 3.3-V
supplies.
The TFP401A incorporates additional circuitry to create a stable HSYNC from DVI transmitters that introduce undesirable jitter on
the transmitted HSYNC signal.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TA
0°C to 70°C
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The TFP401/401A supports display resolutions up to UXGA in 24-bit true color pixel format. The TFP401/401A
offers design flexibility to drive one or two pixels per clock, supports TFT or DSTN panels, and provides an option
for time staggered pixel outputs for reduced ground bounce.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
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Copyright
2000–2003, Texas Instruments Incorporated
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The Texas Instruments TFP401 and TFP401A are TI
PanelBus
flat panel display products, part of a
comprehensive family of end-to-end DVI 1.0 compliant solutions. Targeted primarily at desktop LCD monitors
and digital projectors, the TFP401/401A finds applications in any design requiring high-speed digital interface.
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Supports UXGA Resolution
(Output Pixel Rates Up to 165 MHz)
Digital Visual Interface (DVI) Specification
Compliant
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True-Color, 24 Bit/Pixel, 16.7M Colors at
1 or 2-Pixels Per Clock
Laser Trimmed Internal Termination
Resistors for Optimum Fixed Impedance
Matching
Skew Tolerant Up to One Pixel Clock Cycle
4x Over-Sampling
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Reduced Power Consumption – 1.8 V Core
Operation With 3.3 V I/Os and Supplies
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Reduced Ground Bounce Using Time
Staggered Pixel Outputs
Lowest Noise and Best Power Dissipation
Using TI PowerPAD Packaging
Advanced Technology Using TI 0.18-µm
EPIC-5 CMOS Process
TFP401A Incorporates HSYNC Jitter
Immunity
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