TFP401, TFP401A
TI
PanelBus
DIGITAL RECEIVER
SLDS120B - MARCH 2000 – REVISED JUNE 2003
PARAMETER MEASUREMENT INFORMATION
tr1
QE(0-23), QO(0-23), DE
CTK(1-3), HSYNC, VSYNC
80%
20%
tf1
80%
20%
Figure 1. Rise and Fall TIme of Data and Control Signals
tr2
ODCK
80%
20%
tf2
80%
20%
Figure 2. Rise and Fall Time of ODCK
fODCK
ODCK
Figure 3. ODCK Frequency
18
t(su1)
66
43
41
5
t(su2)
t(h2)
VOH
VOL
t(h1)
ODCK
公
司
OCK_INV
合
讯
金
ODCK
科
Figure 4. Data Setup and Hold Time to Rising and Falling Edge of ODCK
技
VOH
td(st)
50%
tps
Tx+
50%
Tx-
深
圳
市
QE(O-23)
Figure 5. ODCK High to QE[23:0]
Staggered Data Output
有
限
QE(0-23), QO(0-23), DE
CTL(1-3), HSYNC, VSYNC
VOH
VOL
,
VOH
VOL
VOH
VOL
85
,
VOH
VOL
Figure 6. Analog Input Intra-Pair
Differential Skew
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
QQ
VOH
VOL
:
71
44
51
8
9
19