SPI communications operates in slave mode only, and obeys
DRDY control signaling. The clocking is as follows:
New commands attempted during intermediate byte transfers
are ignored.
Clock idle:
High
Wake operation: The device can be put into sleep mode with a
serial command, 0x16 (page 16) and then be awakened later
with a 10µs minimum low level on the WS pin. With the /SS line
tied to WS, the host can simply toggle /SS low for 10µs
minimum to wake the part; the host should not send an actual
SPI byte to prevent the device from seeing a byte it cannot
properly interpret due to timing errors during wakeup.
Clock shift out edge:
Clock data in edge:
Max clock rate:
Falling
Rising
4MHz
SPI mode requires 5 signals to operate:
MOSI - Master out / Slave in data pin; used as an input for data
from the host (master). This pin should be connected to the
MOSI (DO) pin of the host device.
The recommended method to reestablish communications after
Wake from Sleep is to send the QT device a 0x0F ('Get Last
Command' command) repeatedly until the correct response
comes back (the command's own compliment, i.e. 0xF0).
MISO - Master in / Slave out data pin; used as an output for
data to the host. This pin should be connected to the MISO
(DI) pin of the host. MISO floats when /SS is high to allow
multi-drop communications along with other slave parts.
SPI Line Noise: In some designs it is necessary to run SPI
lines over ribbon cable across a lengthy distance on a PCB.
This can introduce ringing, ground bounce, and other noise
problems which can introduce false SPI clocking or false data.
Simple RC networks and slower data rates are helpful to
resolve these issues as shown in Figure 3-2.
SCK - SPI clock - input only clock from host. The host must shift
out data on the falling SCK edge; the QT60xx6 clocks data in
on the rising edge. The QT60xx6 likewise shifts data out on
the falling edge of SCK back to the host so that the host can
shift the data in on the rising edge. Important: SCK must
idle high; it should never float.
CRC checks have also been added to critical commands in
order to detect transmission errors to a high level of certainty.
/SS - Slave select - input only; acts as a framing signal to the
sensor from the host. /SS must be low before and during
reception of data from the host. It must not go high again
until the SCK line has returned high; /SS must idle high. This
pin includes an internal pull-up resistor of 20K ~ 50K. When
/SS is high, MISO floats.
3.3 UART Communications
See also SR setup parameter, page 23.
UART mode is selected as soon as the QT receives any data
on the UART Rx pin. There is no other configuration required to
make the device operate in UART mode. Once UART is
selected after a power-up, the device cannot switch to SPI
mode unless the device is reset.
DRDY - Data Ready - active-high - indicates to the host that the
QT is ready to send or receive data. This pin idles high. This
pin includes an internal pull-up resistor of 20K ~ 50K. In SPI
mode this pin is an output only (i.e. open drain with internal
pull-up).
UART mode communications functions in the same basic way
as SPI communications. The Baud rate is adjusted by means of
setup parameter ‘SR’ (page 23). Once a new Baud rate has
been set, the device must be reset for the new rate to take
effect.
The MISO pin on the QT floats in 3-state mode between bytes
when /SS is high. This facilitates multiple devices on one SPI
bus.
The major difference with SPI mode is that the UART mode is
asynchronous and so the host does not clock the QT. No
framing /SS or clock signal is required, simplifying the interface
greatly. Return data is sent from the QT back to the host when
the data is ready.
Null Bytes: When the QT responds to a command with one or
more response bytes, the host should issue a null commands
(0x00) to get the response bytes back. The host should not
send new commands until all the responses are accepted back
from the QT from the prior command via nulls.
Figure 3-3 SPI Slave-Only Mode Timing (Fosc = 16MHz)
S1: m125ns
S2: [20ns
S3: m25ns
S4: [20ns
S9: m250ns
S5: [20µs S6: m1µs
S7: m125ns
S8: m125ns
S6
high via pullup-R
S1
DRDY
(from QT)
S5
/SS
(from Host)
S3
S9
CLK
(from Host)
S7
5
S8
1
Data shifts in to QT on rising edge
MOSI
?
7
6
5
4
3
2
1
0
7
7
6
6
4
3
2
0
7
6
5
4
3
2
1
0
(Data from Host)
{Command byte}
Data shifts out of QT on falling edge
{optional 2nd command byte}
{null byte or next command to get QT response}
S2
S4
3-state
MISO
(Data from QT)
3-state
?
7
6
5
4
3
2
1
0
?
5
4
3
2
1
0
?
7
6
5
4
3
2
1
0
data response
lQ
12
QT60486-AS R8.01/0105
QUANTUM [ QUANTUM RESEARCH GROUP ]
