© Quantum Research Group Ltd.
Figure 4-2 SPI Slave-Only Mode Timing
T
dr3
T
cm
T
T
dr2
dr1
DRDY
{from sensor}
SS
{from host}
SCK
{from host}
MOSI
{from host}
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Optional Byte 2
Host Command Byte 1
Null Dummy Data
7 6 5 4 3 2 1 0
Null Dummy Data
7 6 5 4 3 2 1 0
MISO
{from sensor}
7 6 5 4 3 2 1 0
Invalid Data
7 6 5 4 3 2 1 0
Invalid Data
Response Data or Echo
Nth Response Data
{N = command dependent}
Figure 4-3 SPI Master/Slave Mode Timing
T
T
T
cm
dr1
dr3
SS
SCK
MOSI
7 6 5 4 3 2 1 0
Command Byte 1
from Host to sensor
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Optional Byte 2
from host to sensor
Response Byte or Echo
from sensor to host
Nth Byte from sensor
{N = command dependent}
SS, SCK, MOSI originate from Host
Floating
SS, SCK, MOSI originate from sensor
interface in both directions. Unlike hardware SPI slaves,
QT60xx5's need processing time to respond to functions.
DRDY’ is used to let the host know when data is ready for
collection; it indicates to the host when data is ready in
response to a command so that the host can clock over the
data.
SS’ transitions either up or down, or the transmission will
fail; between bytes SCK should always idle low. SCK
should never float.
SS’ - Slave select - input only; acts as a framing signal to the
sensor from the host. SS’ must be low before and during
reception of data from the host. It must not go high again
until SCK line has returned low; during data or echo
response it must not go high until after the host has
sensed that DRDY’ has gone high from the device. SS’
must idle high. SS’ has an internal pullup resistor.
This mode requires 5 signals to operate:
MOSI - Master out / Slave in data pin; used as an input for
data from the host at all times. This pin should be
connected to the MOSI pin of the host device.
DRDY’ - Data Ready - active-low - indicates to the host that
the part is ready to send data back subsequent to a
command from the host. This pin idles high. The DRDY’
pin has an internal pullup resistor inside.
MISO - Master in / Slave out data pin; used as an output for
data to the host at all times. This pin should be connected
to the MISO pin of the host device.
SCK - SPI clock - input only clock pin from host. The host
must shift out data on the falling edge of SCK; the
QT60xx5B clocks data in on the rising edge of SCK.
Important note: SCK must idle low just before and after
Internal pullup resistors note: The internal pullup resistors
can range from 35k to 120k ohms. If RC filtering is used on
the SPI lines per Figure 4-4, this resistance may not be low
Table 4-1 Typical DRDY (Tdr1) Response Delays (Burst Length = 12)
Burst Spacing
Function Type
Setup - Put (affect 1 key)
250µs
10ms
40ms
300ms
800ms
3ms
300µs
10ms
40ms
300ms
800ms
2.7ms
1ms
400µs
500µs
10ms
1ms
10ms
40ms
300ms
800ms
2ms
2ms
10ms
40ms
300ms
800ms
2ms
10ms
40ms
40ms
Setup - Put (affect 8 keys)
Setup - Put (affect 64 keys)
Lock Reference Levels ('L') command
Calibrate command (all keys)
Get key errors (E), Get keys pushed (K)
All other commands
300ms
800ms
2.5ms
800us
300us
300ms
800ms
2.5ms
800us
300us
1ms
800us
300us
800us
300us
400us
300us
lQ
17
www.qprox.com QT60xx5B / R1.06
QUANTUM [ QUANTUM RESEARCH GROUP ]
