C is the load Cx. If the series-R or Cx is too large, sensitivity
will be reduced.
5. Route sense traces away from other traces or wires that
are connected to other circuits.
Directly placing semiconductor transient protection devices
or MOV's on the sense leads is not advised; these devices
have extremely large amounts of non-linear parasitic C,
which will swamp the capacitance of the electrode and may
deliver spurious sensing results.
6. Sense electrodes should be kept away from other
circuits and grounds which are not directly connected to
the sensor’s own circuit ground; other grounds will
appear to float at high frequencies and couple RF
currents into the sense lines.
7. Keep the Cs sampling capacitors and all series-R
components close to the IC.
5.4 RF Susceptibility
PCB layout, grounding, and the structure of the input circuitry
have a great bearing on the success of a design that can
withstand strong RF interference. The circuit is remarkably
immune to RFI provided that certain design rules are
adhered to:
8. Use a 0.1µF minimum, ceramic bypass cap very close to
the VSS/VDD supply pins.
9. Use series-R’s in the sense line of as large a value as
the circuit can tolerate without degrading sensitivity
appreciably (see Section 1.2).
1. Use SMT components to minimize lead lengths.
2. Connect electrodes to SNS1, not SNS2.
10. Bypass input power to chassis ground and again at
circuit ground to reduce line-injected noise effects.
Ferrites over the power wiring may be required to
attenuate line injected noise.
3. Use a ground plane under and around the circuit and
along the sense lines, that is as unbroken as possible
except for relief under and beside the sense lines to
reduce total Cx. Relieved rear ground planes along the
SNS lines should be ‘mended’ by bridging over them at
1cm intervals with 0.5mm ‘rungs’ like a ladder.
Achieving RF immunity requires diligence and a good
working knowledge of grounding, shielding, and layout
techniques. Very few projects involving these devices will fail
EMC tests once properly constructed.
4. Ground planes and traces should be connected only to a
common point near the VSS pin of the IC.
LQ
6
QT301 R1.06 12/03
QUANTUM [ QUANTUM RESEARCH GROUP ]
