Contents
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Table 1.1 Scanport / UART Pinlist
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Table 1.2 Standalone Pinlist
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Table 1.3 Standalone Pinlist
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Table 1.4 SPI Pinlist
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Table 1.5 Pin Descriptions
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Figure 1.1 SPI Connection Diagram
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Figure 1.2 UART / Scanport Connection Diagram
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Figure 1.3 Scanport Only Connection Diagram+
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2 Device Control & Wiring
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2.1 Oscillator
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2.2 Spread Spectrum Modulation
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2.3 Cs Sample Capacitors
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2.4 Sensitivity
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2.5 Sensitivity Balance
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2.6 Power Supply
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2.7 PCB Layout and Construction
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2.8 ESD Protection
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2.9 Noise Issues
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2.9.1 LED Traces and Other Switching Signals
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2.9.2 External Fields
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2.10 Start-up Time
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2.11 Operating Parameter Setups
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2.12 Standalone Operation, No EEPROM
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2.13 EEPROM Functionality
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2.14 Scanport Interface
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2.15 Start-up Sequencing
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2.16 Error Detection and Reporting
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3 Serial Operation
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3.1 UART Interface
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3.1.1 TX Pin
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3.1.2 Sleep/Wake Operation in UART Mode
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3.1.3 CRDY Operation in UART Mode
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3.2 SPI Operation
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3.2.1 Multi-Drop SPI Capability
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3.2.2 Sleep/Wake Operation in SPI Mode
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3.2.3 CRDY Operation in SPI Mode
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3.3 Communication Error Handling
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3.4 Control Commands
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3.4.1 Null Command - 0x00
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3.4.2 Enter Setups Load Mode - 0x01
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3.4.3 Enter Run Mode - 0x02
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3.4.4 Enter Cal Mode - 0x03
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3.4.5 Force Reset - 0x04
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3.4.6 Sleep - 0x05
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3.4.7 Cal Key ‘k’ - 0x1k
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3.5 Status Commands
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3.5.1 Signal for 1 Key - 0x2k
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3.5.2 Reference for Key ‘k’ - 0x4k
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1 Overview
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3.5.5 Report 1st Key - 0xC0
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3.5.6 Report All Keys - 0xC1
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3.5.7 Device Status - 0xC2
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3.5.8 EEPROM CRC - 0xC3
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3.5.9 RAM CRC - 0xC4
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3.5.10 Error Flags for Group - 0xC5
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3.5.11 Internal Code - 0xC6
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3.5.12 Return Last Command - 0xC7
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3.5.13 Dump Setups Block - 0xC8
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3.5.14 Quick Report First Key - 0xC9
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3.6 Command Sequencing
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Figure 3-1 Suggested Serial Flow
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Table 3-1 Control Commands
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Table 3-2 Status Commands
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4 Setup Block Functions
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4.1 NTHR - Negative Threshold Bits
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4.2 NHYS - Negative Hysteresis Bits
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4.3 NDCR / PDCR - Drift Comp Bits
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4.4 NRD - Negative Recal Delay Bits
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4.5 PRD - Positive Recal Delay Bits
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4.6 AKS - Adjacent Key Suppression Bits
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4.7 EK - Error Key Control Bits
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4.8 K2L / LEDP / KEYO Control Bits
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4.9 NDIL, FDIL - Detect Integrator Bits
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4.10 PTHR - Positive Threshold Bits
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4.11 PHYS - Positive Hysteresis Bits
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4.12 SE, SYNC Control Bits
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4.13 LBLL - Lower Burst Length Limit
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4.14 BS - Burst Spacing Control Bits
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4.15 BR - Baud Rate Control Bits
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4.16 HCRC - Host CRC
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Table 4-1 Serial / EEPROM Setups Block
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4.17 Timing Tables
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5 - Specifications
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5.1 Absolute Maximum Specifications
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5.2 Recommended Operating Conditions
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5.3 AC Specifications
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5.4 DC Specifications
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5.5 Burst / Sync Timing
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5.6 SPI Timing Diagram
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5.7 QT1100A Timing Parameters - with Fosc = 12MHz
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5.8 Current vs Vdd
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5.9 Mechanical
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5.10 Marking
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6 Appendix A - 8-Bit CRC C Algorithm
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3.5.3 Detect Integrator for Key ‘k’ - 0x6k
3.5.4 Status for Key ‘k’ - 0x8k
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LQ
2
Copyright © 2003-2005 QRG Ltd
QT1100A-ISG R3.02/1105
QUANTUM [ QUANTUM RESEARCH GROUP ]
