QN8006B/8006LB
Word: STATUS3 Address: 1Bh (RO)
Bit 7
Bit 0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(MSB)
rds_rxtxupd
ro
(LSB)
rdsd3err
ro
e_det
ro
rdsc0c1
ro
rdssync
ro
rdsd0err
ro
rdsd1err
ro
rdsd2err
ro
Bit
Symbol
Default
Description
7
RDS_RXTXUPD
r
RDS RX: RDS received group updated. Each time a new group is
received, this bit will be toggled.
RDS TX: If the user wants the chip to transmit all of the 8 bytes in
RDS0~RDS7, the user should toggle the register bit RDSTXRDY. Then
the chip internally will fetch these bytes after completing transmission of
the current group. Once the chip internally has fetched these bytes, it will
toggle this bit.
If RDS_INT_EN=1, then at the same time this bit is toggled, the interrupt
output pin (INT) will output a 4.5 ms low pulse.
0->1 or 1->0 A new set (8 bytes) of data is received.
0->0 or 1->1 New data is in receiving.
‘E’ block (MMBS block) detected:
6
5
4
3
2
1
0
E_DET
r
r
r
r
r
r
r
0
1
Not detected
Detected
RDSC0C1
RDSSYNC
RDS0ERR
RDS1ERR
RDS2ERR
RDS3ERR
Type indicator of the RDS third block in one group:
0
1
C0
C1
RDS block synchronous indicator:
0
1
Non-synchronous
Synchronous
Received RDS block 0 status indicator:
0
1
No error
Error
Received RDS block 1 status indicator:
0
1
No error
Error
Received RDS block 2 status indicator:
0
1
No error
Error
Received RDS block 3 status indicator:
Rev 2.08 (04/10)
Copyright ©2010 by Quintic Corporation
Page 49
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