QN8006B/8006LB
4.7 RDS/RBDS
The QN8006 supports RDS/RBDS data transmitting and receiving, including station ID, Meta data, TMC information, etc.
The integrated RDS processor performs all symbol encoding/decoding, block synchronization, error detection and
correction functions. RDS/RBDS data communicates with an external MCU through the serial control interface.
When the chip is used as an FM receiver, the internal RDS buffer (the entire RDS Group (8 bytes) is full, an Interrupt signal
is generated. The signal waveform is shown in Figure 10. The user can also check the RDS buffer space by reading the
RDS_RXTXUPD bit in the STATUS2 register (reg. 1Bh [7]).
When the chip is used as an FM transmitter (RDS TX), ping-pong buffers are used so that the user can write into one buffer
while the RDS data in the other buffer is being transmitted. When the internal RDS buffer (8 bytes) is full, an Interrupt
signal is generated. The signal waveform is shown in Figure 10. The user should wait for the Interrupt signal (INT) before
toggling the RDSTXRDY bit in the SYSTEM2 register (reg. 01h [2]). Alternatively, the user can also check the RDS
buffer space by reading the RDS_RXTXUPD bit in the STATUS2 register (reg. 1Bh [7]).
4.55ms
INT
Figure 10: Interrupt Output
RDS/RSBS is not available in the QN8006LB.
Rev 2.08 (04/10)
Copyright ©2010 by Quintic Corporation
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