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HYS72T256220HR-3S-A 参数 Datasheet PDF下载

HYS72T256220HR-3S-A图片预览
型号: HYS72T256220HR-3S-A
PDF下载: 下载PDF文件 查看货源
内容描述: 240引脚注册DDR2 SDRAM模组 [240-Pin Registered DDR2 SDRAM Modules]
分类和应用: 存储内存集成电路动态存储器双倍数据速率
文件页数/大小: 74 页 / 4051 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A  
Registered DDR2 SDRAM Modules  
1.2  
Description  
The QIMONDA HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A  
module family are Registered DIMM modules “RDIMMs” with  
30 mm height based on DDR2 technology. DIMMs are  
available as ECC modules in 64M x 72 (512 MByte),  
128M x 72 (1 GByte) and 256M x 72 (2 GByte) organization  
and density, intended for mounting into 240-Pin connector  
sockets.  
capacitive loading to the system bus, but adds one cycle to  
the SDRAM timing. Decoupling capacitors are mounted on  
the PCB board. The DIMMs feature serial presence detect  
based on a serial E2PROM device using the 2-pin I2C  
protocol. The first 128 bytes are programmed with  
configuration data and the second 128 bytes are available to  
the customer.  
The memory array is designed with 512-Mbit Double-Data-  
Rate-Two (DDR2) Synchronous DRAMs. All control and  
address signals are re-driven on the DIMM using register  
devices and a PLL for the clock distribution. This reduces  
TABLE 2  
Ordering Information for RoHS Compliant Products  
Product Type1)  
Compliance Code2)  
Description  
SDRAM Technology  
PC2-5300  
HYS72T64000HR–3–A  
HYS72T128000HR–3–A  
HYS72T128020HR–3–A  
HYS72T256220HR–3–A  
HYS72T64000HR–3S–A  
HYS72T128000HR–3S–A  
HYS72T128020HR–3S–A  
HYS72T256220HR–3S–A  
HYS72T256040HR–3S–A  
PC2–4200  
512 MB 1R×8 PC2–5300R–444–12–F0  
1 GB 1R×4 PC2–5300R–444–12–H0  
1 GB 2R×8 PC2–5300R–444–12–G0  
2 GB 2R×4 PC2–5300R–444–12–J1  
512 MB 1R×8 PC2–5300R–555–12–F0  
1 GB 1R×4 PC2–5300R–555–12–H0  
1 GB 2R×8 PC2–5300R–555–12–G0  
2 GB 2R×4 PC2–5300R–555–12–J1  
2 GB 4R×4 PC2–5300R–555–12–N0  
1 Rank, ECC  
1 Rank, ECC  
512 Mbit (×8)  
512 Mbit (×4)  
2 Ranks, ECC 512 Mbit (×8)  
2 Ranks, ECC 512 Mbit (×4)  
1 Rank, ECC  
1 Rank, ECC  
512 Mbit (×8)  
512 Mbit (×4)  
2 Ranks, ECC 512 Mbit (×8)  
2 Ranks, ECC 512 Mbit (×4)  
4 Ranks, ECC 512 Mbit (×8)  
HYS72T64000HR–3.7–A  
HYS72T128000HR–3.7–A  
HYS72T128020HR–3.7–A  
HYS72T256220HR–3.7–A  
HYS72T256040HR–3.7–A  
PC2-3200  
512 MB 1R×8 PC2–4200R–444–12–F0  
1 GB 1R×4 PC2–4200R–444–12–H0  
1 GB 2R×8 PC2–4200R–444–12–G0  
2 GB 2R×4 PC2–4200R–444–12–J1  
2 GB 4R×8 PC2–4200R–444–12–N0  
1 Rank, ECC  
1 Rank, ECC  
512 Mbit (×8)  
512 Mbit (×4)  
2 Ranks, ECC 512 Mbit (×8)  
2 Ranks, ECC 512 Mbit (×4)  
4 Ranks, ECC 512 Mbit (×8)  
HYS72T64000HR–5–A  
HYS72T128000HR–5–A  
HYS72T128020HR–5–A  
HYS72T256220HR–5–A  
512 MB 1R×8 PC2–3200R–333–12–F0  
1 GB 1R×4 PC2–3200R–333–12–H0  
1 GB 2R×8 PC2–3200R–333–12–G0  
2 GB 2R×4 PC2–3200R–333–12–J1  
1 Rank, ECC  
1 Rank, ECC  
512 Mbit (×8)  
512 Mbit (×4)  
2 Ranks, ECC 512 Mbit (×8)  
2 Ranks, ECC 512 Mbit (×4)  
1) Product Type numbers end with a place code, designating the silicon die revision. Example: HYS72T64000HR–3.7–A, indicating Rev. “A”  
dies are used for DDR2 SDRAM components. For all QIMONDA DDR2 module and component nomenclature see Table 6 of this data  
sheet.  
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200R–444–12–F0”, where  
4200R means Registered DIMM modules with 4.26 GB/sec Module Bandwidth and “444-11” means Column Address Strobe (CAS) latency  
= 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2 and produced  
on the Raw Card “F”  
Rev. 1.31, 2006-11  
4
03292006-21GC-MK06  
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