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HYS64T32000EDL-3.7-B2 参数 Datasheet PDF下载

HYS64T32000EDL-3.7-B2图片预览
型号: HYS64T32000EDL-3.7-B2
PDF下载: 下载PDF文件 查看货源
内容描述: 200针SO -DIMM DDR2 SDRAM模组 [200-Pin SO-DIMM DDR2 SDRAM Modules]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 86 页 / 4614 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2  
Small Outlined DDR2 SDRAM Modules  
3.4  
IDD Specifications and Conditions  
List of tables defining IDD Specifications and Conditions.  
Table 20 “IDD Measurement Conditions” on Page 28  
Table 21 “Definitions for IDD” on Page 29  
Table 22 “IDD Specification for HYS64T[32/64/128]xxxEDL–25F–B2” on Page 30  
Table 23 “IDD Specification for HYS64T[32/64/128]xxxEDL–2.5–B2” on Page 31  
Table 24 “IDD Specification for HYS64T[32/64/128]xxxEDL–3–B2” on Page 32  
Table 25 “IDD Specification for HYS64T[32/64/128]xxxEDL–3S–B2” on Page 33  
Table 26 “IDD Specification for HYS64T[32/64/128]xxxEDL–3.7–B2” on Page 34  
TABLE 20  
DD Measurement Conditions  
I
Parameter  
Symbol Note  
1)2)3)4)5)  
Operating Current 0  
IDD0  
One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between  
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.  
6)  
Operating Current 1  
IDD1  
One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN  
,
t
RCD = tRCD.MIN, AL = 0, CL = CLMIN; CKE is HIGH, CS is HIGH between valid commands. Address and  
control inputs are SWITCHING, Databus inputs are SWITCHING.  
Precharge Standby Current  
IDD2N  
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are SWITCHING,  
Databus inputs are SWITCHING.  
Precharge Power-Down Current  
Other control and address inputs are STABLE, Data bus inputs are FLOATING.  
IDD2P  
IDD2Q  
Precharge Quiet Standby Current  
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE,  
Data bus inputs are FLOATING.  
Active Standby Current  
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN  
IDD3N  
;
t
RAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are  
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.  
Active Power-Down Current  
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs  
are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);  
IDD3P(0)  
IDD3P(1)  
IDD4R  
Active Power-Down Current  
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs  
are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);  
6)  
Operating Current - Burst Read  
All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCKMIN; tRAS = tRASMAX  
;
t
RP = tRPMIN; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data  
bus inputs are SWITCHING; IOUT = 0mA.  
Operating Current - Burst Write  
IDD4W  
All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN  
;
t
RAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are  
SWITCHING; Data Bus inputs are SWITCHING;  
Rev. 1.1, 2007-01  
28  
08212006-PKYN-2H1B  
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