Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
TABLE 17
DRAM Component Timing Parameter by Speed Grade - DDR2–533
Parameter
Symbol
DDR2–533
Unit
Note1)2)3)4)5)
6)7)
Min.
Max.
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
tAC
–500
2
+500
—
ps
—
—
—
—
tCCD
tCH
tCKE
tCL
tCK
tCK
tCK
tCK
tCK
0.45
3
0.55
—
CKE minimum high and low pulse width
CK, CK low-level width
0.45
WR + tRP
0.55
—
—
8)18)
Auto-Precharge write recovery + precharge
time
tDAL
9)
Minimum time clocks remain ON after CKE
asynchronously drops LOW
tDELAY
tIS + tCK + tIH
225
––
––
—
ns
ps
ps
10)
11)
DQ and DM input hold time (differential data
strobe)
t
t
DH (base)
DQ and DM input hold time (single ended data
strobe)
DH1 (base)
–25
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
tDIPW
0.35
–450
0.35
—
—
tCK
ps
tCK
ps
—
—
tDQSCK
+450
—
DQS input low (high) pulse width (write cycle) tDQSL,H
—
11)
DQS-DQ skew (for DQS & associated DQ
signals)
tDQSQ
300
Write command to 1st DQS latching transition tDQSS
– 0.25
100
+ 0.25
—
tCK
—
11)
DQ and DM input setup time (differential data
strobe)
t
DS (base)
ps
11)
DQ and DM input setup time (single ended data tDS1 (base)
strobe)
–25
0.2
—
—
—
ps
DQS falling edge hold time from CK (write
cycle)
tDSH
tCK
tCK
—
DQS falling edge to CK setup time (write cycle) tDSS
0.2
—
12)
Clock half period
tHP
MIN. (tCL, tCH)
13)
11)
Data-out high-impedance time from CK / CK
Address and control input hold time
tHZ
—
tAC.MAX
—
ps
ps
tCK
tIH(base)
tIPW
375
0.6
Address and control input pulse width
(each input)
—
—
11)
14)
14)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
tIS(base)
tLZ(DQ)
tLZ(DQS)
tMRD
250
—
ps
ps
ps
tCK
ns
2 × tAC.MIN
tAC.MAX
tAC.MAX
—
tAC.MIN
2
0
—
—
—
—
tOIT
12
Data output hold time from DQS
Data hold skew factor
tQH
t
HP –tQHS
—
tQHS
—
400
ps
Rev. 1.1, 2007-01
24
08212006-PKYN-2H1B