Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
3.3.2
Timing Parameters
Timing Parameters: Table 15 for DDR2–800; Table 16 for DDR2–667 and Table 17 for DDR2–533C.
TABLE 15
DRAM Component Timing Parameter by Speed Grade - DDR2–800
Parameter
Symbol
DDR2–800
Unit
Note1)2)3)4)5)6)7)
8)
Min.
Max.
9)
DQ output access time from CK / CK
DQS output access time from CK / CK
Average clock high pulse width
Average clock low pulse width
Average clock period
tAC
–400
–350
0.48
+400
+350
0.52
0.52
8000
––
ps
9)
tDQSCK
tCH.AVG
tCL.AVG
tCK.AVG
tDS.BASE
tDH.BASE
ps
10)11)
10)11)
10)11)
12)13)14)
13)14)15)
tCK.AVG
tCK.AVG
ps
0.48
2500
50
DQ and DM input setup time
DQ and DM input hold time
ps
125
––
ps
Control & address input pulse width for each input tIPW
0.6
—
tCK.AVG ––
tCK.AVG ––
DQ and DM input pulse width for each input
Data-out high-impedance time from CK / CK
DQS/DQS low-impedance time from CK / CK
DQ low impedance time from CK/CK
tDIPW
tHZ
tLZ.DQS
tLZ.DQ
0.35
—
9)16)
—
tAC.MAX
tAC.MAX
tAC.MAX
200
ps
ps
ps
ps
ps
9)16)
9)16)
17)
tAC.MIN
2 x tAC.MIN
—
DQS-DQ skew for DQS & associated DQ signals tDQSQ
18)
CK half pulse width
tHP
Min (tCH.ABS
,
__
tCL.ABS
)
19)
20)
DQ hold skew factor
tQHS
tQH
—
300
—
ps
DQ/DQS output hold time from DQS
t
HP – tQHS
ps
Write command to DQS associated clock edges WL
RL – 1
– 0.25
nCK
tCK.AVG
––
21)
DQS latching rising transition to associated clock tDQSS
+ 0.25
edges
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Write postamble
tDQSH
tDQSL
tDSS
0.35
0.35
0.2
—
—
—
—
0.6
—
—
—
1.1
0.6
—
—
—
—
tCK.AVG ––
tCK.AVG ––
21)
tCK.AVG
21)
tDSH
0.2
tCK.AVG
tWPST
tWPRE
tIS.BASE
tIH.BASE
tRPRE
tRPST
tCCD
0.4
tCK.AVG ––
Write preamble
0.35
175
250
0.9
tCK.AVG ––
22)23)
Address and control input setup time
Address and control input hold time
Read preamble
ps
23)24)
25)26)
25)27)
ps
tCK.AVG
tCK.AVG
nCK
ns
Read postamble
0.4
CAS to CAS command delay
Write recovery time
2
––
1)
tWR
15
28)29)
1)30)
Auto-Precharge write recovery + precharge time tDAL
WR + tnRP
7.5
nCK
ns
Internal write to read command delay
tWTR
Rev. 1.1, 2007-01
17
08212006-PKYN-2H1B
QIMONDA [ QIMONDA AG ]
