Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Parameter
Symbol
DDR2–667
Unit
Notes1)2)3)4)5)6)
7)8)
Min.
Max.
28)
28)
Active to active command period for 1KB page
size products
tRRD
tRRD
7.5
—
ns
ns
Active to active command period for 2KB page
size products
10
—
28)
28)
Four Activate Window for 1KB page size products tFAW
Four Activate Window for 2KB page size products tFAW
37.5
—
—
—
—
—
—
—
—
—
—
ns
50
ns
CAS to CAS command delay
Write recovery time
tCCD
tWR
2
nCK
ns
28)
15
29)30)
28)31)
28)
Auto-Precharge write recovery + precharge time tDAL
WR + tnRP
7.5
nCK
ns
Internal write to read command delay
Internal Read to Precharge command delay
Exit self-refresh to a non-read command
Exit self-refresh to read command
tWTR
tRTP
tXSNR
tXSRD
tXP
7.5
ns
28)
t
RFC +10
ns
200
2
nCK
nCK
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit power down to read command
tXARD
2
—
—
nCK
nCK
Exit active power-down mode to read command tXARDS
7 – AL
(slow exit, lower power)
32)
CKE minimum pulse width ( high and low pulse tCKE
width)
3
—
2
nCK
ODT turn-on delay
tAOND
tAON
2
nCK
ns
9)33)
ODT turn-on
tAC.MIN
t
AC.MAX + 0.7
2 x tCK.AVG
AC.MAX + 1
2.5
AC.MAX + 0.6
2.5 x tCK.AVG
AC.MAX + 1
ODT turn-on (Power down mode)
tAONPD
t
AC.MIN + 2
+
ns
t
ODT turn-off delay
tAOFD
tAOF
2.5
nCK
ns
34)35)
ODT turn-off
tAC.MIN
t
ODT turn-off (Power down mode)
tAOFPD
t
AC.MIN + 2
+
ns
t
ODT to power down entry latency
ODT to power down exit latency
Mode register set command cycle time
MRS command to ODT update delay
OCD drive mode output delay
tANPD
tAXPD
tMRD
tMOD
tOIT
3
8
2
0
0
––
nCK
nCK
nCK
ns
—
12
12
––
1)
1)
ns
Minimum time clocks remain ON after CKE
asynchronously drops LOW
tDELAY
t
LS + tCK .AVG
+
ns
tLH
1) For details and notes see the relevant Qimonda component data sheet
2)
DDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V. See notes 5)6)7)8)
V
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
Rev. 1.41, 2007-05
21
03292006-EZUJ-JY4S
QIMONDA [ QIMONDA AG ]
