Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
2
Pin Configuration
The pin configuration of the Unbuffered DDR SDRAM DIMM
is listed by function in Table 3 (184 pins). The abbreviations
used in columns Pin and Buffer Type are explained in Table 4
and Table 5 respectively. The pin numbering is depicted in
Figure 1.
TABLE 3
Pin Configuration of UDIMM
Pin#
Name
Pin
Type
Buffer
Type
Function
Clock Signals
137
CK0
I
SSTL
–
Clock Signals 2:0
NC
NC
16
CK1
CK2
CK0
NC
I
SSTL
SSTL
SSTL
–
76
I
138
I
Complement Clock Signals 2:0
NC
17
CK1
CK2
CKE0
CKE1
I
I
I
I
SSTL
SSTL
SSTL
SSTL
75
21
Clock Enable Rank 0
Clock Enable Rank 1
Note: 2-rank module
Note: 1-rank module
111
NC
NC
–
Control Signals
157
158
S0
S1
I
I
SSTL
SSTL
Chip Select Rank 0
Chip Select Rank 1
Note: 2-rank module
Note: 1-rank module
Row Address Strobe
Column Address Strobe
Write Enable
NC
NC
–
154
65
RAS
CAS
WE
I
I
I
SSTL
SSTL
SSTL
63
Rev. 1.22, 2007-01
5
03292006-CXBY-V2JX
QIMONDA [ QIMONDA AG ]
