Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
1
Overview
This chapter contains features and the description.
1.1
Features
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184-Pin Unbuffered Double-Data-Rate Memory Modules
(ECC and non-parity) for PC and Workstation main
memory applications
One rank 32M × 64, 64M x 64, 64M ×72 and two ranks
128M × 64, 128M ×72 organization
standard Double Data Rate Synchronous DRAMs Single
+2.5V (± 0.2V) power supply
Built with 512-Mbit in P-TSOPII-66 package
Programmable CAS Latency, Burst Length, and Wrap
Sequence (Sequential & Interleave)
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Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_2 compatible
Serial Presence Detect with E2PROM
JEDEC standard MO-206 form factor:
133.35 mm × 31.75 mm × 4.00 mm max.
Standard reference layout
Gold plated contacts
DDR400 speed grade supported
Lead-free
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TABLE 1
Performance for –5 and –6
Part Number Speed Code
–5
–6
Unit
Speed Grade
Component
Module
@CL3
DDR400B
PC3200 - 3033
200
DDR333B
PC2700 - 2533
166
—
—
Max. Clock Frequency
fCK3
MHz
MHz
MHz
@CL2.5
@CL2
fCK2.5
fCK2
166
166
133
133
1.2
Description
The Qimonda HYS64D32301[G/H]U–5–B, HYS[64/72]D64xxx[G/H]U–
[5/6]–B and HYS[64/72]D128xxx[G/H]U–[5/6]–B are industry standard
184-Pin Unbuffered Double-Data-Rate Memory Modules (UDIMM)
organized as 32M × 64M (256 MB), 64M ×64 (512 MB),
128M ×64 (1 GB) for non-parity and 64M ×72 (512 MB),
128M ×72 (1 GB) for ECC main memory applications. The
memory array is designed with 512Mbit Double Data Rate
Synchronous DRAMs. A variety of decoupling capacitors are
mounted on the printed circuit board. The DIMMs feature
serial presence detect (SPD) based on a serial E2PROM
device using the 2-pin I2C protocol. The first 128 bytes are
programmed with configuration data and the second
128 bytes are available to the customer.
Rev. 1.22, 2007-01
3
03292006-CXBY-V2JX
QIMONDA [ QIMONDA AG ]
