Internet Data Sheet
HY[B/I]39SC256[80/16]0F[E/F]
256-MBit Synchronous DRAM
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TABLE 5
Mode Register Definition (BA[1:0] = 00B)
Field
BL
Bits
Type
Description
Burst Length
[2:0]
w
Number of sequential bits per DQ related to one read/write command, see Table 6
Note: All other bit combinations are RESERVED
000B
001B
010B
011B
1
2
4
8
111B Full Page (Sequential burst type only)
BT
CL
3
Burst Type
0B
1B
Sequential
Interleaved
[6:4]
CAS Latency
Number of full clocks from read command to first data valid window.
Note: All other bit combinations are RESERVED.
010B
011B
2
3
TM
[8:7]
Test Mode
Note: All other bit combinations are RESERVED.
00B Mode register set
WBL
9
Write Burst Length
0B
1B
Burst write
Single bit write
[12:10]
Reserved, set to zero
Rev. 1.25, 2007-06
03062006-NMGU-CQ9D
11
QIMONDA [ QIMONDA AG ]
