Internet Data Sheet
HY[B/I]39SC128[800/160]FE
128-MBit Synchronous DRAM
Parameter
Symbol
–7
–6
Unit Note1)2)
3)
PC133–222
PC166–333
Min.
Max.
Min.
Max.
6)
CKE Hold Time
tCKH
tRSC
tSB
0.8
2
—
—
7
0.8
2
—
—
6
ns
Mode Register Set-up to Active delay
Power Down Mode Entry Time
Common Parameters
tCK
0
0
ns
7)
7)
7)
7)
Row to Column Delay Time
Row Precharge Time
tRCD
tRP
tRAS
tRC
15
15
37
60
63
14
1
—
15
15
36
60
60
12
1
—
ns
ns
ns
ns
ns
ns
tCK
—
—
Row Active Time
100k
—
100k
—
Row Cycle Time
Row Cycle Time during Auto Refresh
Activate(a) to Activate(b) Command period
CAS(a) to CAS(b) Command period
Refresh Cycle
tRFC
tRRD
tCCD
—
—
7)
—
—
—
—
Refresh Period (4096 cycles)
Self Refresh Exit Time
tREF
tSREX
tOH
–
1
3
64
—
—
–
64
—
—
ms
tCK
ns
1
3)5)
Data Out Hold Time
2.5
Read Cycle
Data Out to Low Impedance Time
Data Out to High Impedance Time
DQM Data Out Disable Latency
Write Cycle
tLZ
0
—
7
0
—
6
ns
ns
tCK
tHZ
3
3
tDQZ
—
2
—
2
8)
9)
Last Data Input to Precharge
(Write without Auto Precharge)
tWR
14
—
0
—
—
—
12
—
0
—
—
—
ns
Last Data Input to Activate
(Write with Auto Precharge)
tDAL(min.)
tDQW
tCK
tCK
DQM Write Mask Latency
1) TA = 0 to 70 °C; VSS = 0 V; VDD, VDDQ = 3.3 V ± 0.3 V, tT = 1 ns
2) For proper power-up see the operation section of this data sheet.
3) AC timing tests for LV-TTL versions have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition
time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown in figure below.
Specified tAC and tOH parameters are measured with a 50 pF only, without any resistive termination and with an input signal of 1V / ns edge
rate between 0.8 V and 2.0 V.
4) If clock rising time is longer than 1 ns, a time (tT/2 - 0.5) ns has to be added to this parameter.
5) Access time from clock tac is 4.6 ns for PC133 components with no termination and 0 pF load,
Data out hold time toh is 1.8 ns for PC133 components with no termination and 0 pF load.
6) If tT is longer than 1 ns, a time (tT - 1) ns has to be added to this parameter.
7) These parameter account for the number of clock cycles and depend on the operating frequency of the clock, as follows:
the number of clock cycles = specified value of timing period (counted in fractions as a whole number)
8) It is recommended to use two clock cycles between the last data-in and the precharge command in case of a write command without Auto-
Precharge. One clock cycle between the last data-in and the precharge command is also supported, but restricted to cycle times tCK greater
or equal the specified tWR value, where tck is equal to the actual system clock time.
9) When a Write command with Auto Precharge has been issued, a time of tDAL(min) has be fullfilled before the next Activate Command can
be applied. For each of the terms, if not already an integer, round up to the next highest integer. tCK is equal to the actual system clock time.
Rev. 1.1, 2007-02
14
09072006-N4GC-EREN
QIMONDA [ QIMONDA AG ]
