Internet Data Sheet
HY[B/I]39SC128[800/160]FE
128-MBit Synchronous DRAM
TABLE 11
IDD Specifications and Conditions
Symbol
Test Condition
RC = tRC(min), IO = 0 mA
–6
–7
Unit
Note 1)
2)3)
IDD1
t
100 80
mA
mA
mA
mA
mA
mA
1)
IDD2P
IDD2N
IDD3N
IDD3P
IDD4
CS =VIH (min.), CKE ≤VIL(max)
CS =VIH (min.), CKE≥ VIH(min)
CS = VIH(min), CKE ≥VIH(min.)
CS = VIH(min), CKE ≤ VIL(max.)
—
2
2
1)
26
40
5
22
35
5
1)
1)
1)3)
4)
65
57
IDD5
t
t
RFC= tRFC(min)
RFC= 15.6 µs
168 142 mA
25
3
25
3
mA
mA
mA
IDD6
—
Standard components
0.8
0.8
Low power components , at 85 °C
1)
2) These parameters depend on the cycle rate. All values are measured at 133 MHz for -7 with the outputs open. Input signals are changed
once during tCK
VSS = 0 V; VDD, VDDQ = 3.3 V ± 0.3 V, TA see Table 7
.
3) These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3 and BL=4 is assumed and
the VDDQ current is excluded.
4)
tRFC= tRFC(min) “burst refresh”, tRFC= 15.6 µs “distributed refresh”.
4.2
AC Characteristics
TABLE 12
AC Timing - Absolute Specifications
Parameter
Symbol
–7
–6
Unit Note1)2)
3)
PC133–222
PC166–333
Min.
Max.
Min.
Max.
Clock and Clock Enable
Clock Frequency
tCK
tAC
—
—
–7
–7.5
—
—
–6
–7.5
ns
ns
CL3
CL2
Access Time from Clock
—
—
5.4
5.4
—
—
5.4
5.4
ns
ns
CL3
CL2
3)4)5)
Clock High Pulse Width
Clock Low Pulse Width
Transition time
tCH
tCL
tT
2.5
2.5
0.3
—
2
—
ns
ns
ns
—
2
—
1.2
0.3
1.2
Setup and Hold Times
Input Setup Time
6)
6)
6)
tIS
1.5
0.8
1.5
—
—
—
1.5
0.8
1.5
—
—
—
ns
ns
ns
Input Hold Time
tIH
tCK
CKE Setup Time
Rev. 1.1, 2007-02
13
09072006-N4GC-EREN
QIMONDA [ QIMONDA AG ]
