Internet Data Sheet
HY[B/I]39SC128[800/160]FE
128-MBit Synchronous DRAM
%$ꢀ %$ꢊ $ꢀꢂ $ꢀꢀ $ꢀꢊ $ꢉ
$ꢈ
$ꢇ
$ꢆ
$ꢅ
&/
$ꢄ
$ꢃ
%7
$ꢂ
$ꢀ
%/
$ꢊ
:%/
70
ꢊ
ꢊ
ꢊ
ꢊ
ꢊ
Z
Z
Z
Z
UHJꢌꢁDGGU
03%6ꢊꢊꢊꢀ
TABLE 5
Mode Register Definition (BA[1:0] = 00B)
Field
BL
Bits
Type
Description
[2:0]
w
Burst Length
Number of sequential bits per DQ related to one read/write command, see
Table 6.
Note: All other bit combinations are RESERVED
000B
001B
010B
011B
1
2
4
8
111B Full Page (Sequential burst type only)
BT
CL
3
Burst Type
0B
1B
Sequential
Interleaved
[6:4]
CAS Latency
Number of full clocks from read command to first data valid window.
Note: All other bit combinations are RESERVED.
010B
011B
2
3
TM
[8:7]
Test Mode
Note: All other bit combinations are RESERVED.
00B Mode register set
WBL
9
Write Burst Length
0B
1B
Burst write
Single bit write
—
[12:10]
Reserved, set to zero
TABLE 6
Burst Length and Sequence
Burst Length
Starting Column Address
Order of Accesses Within a Burst
A2
A1
A0
Type=Sequential
Type=Interleaved
2
—
—
—
—
0
1
0–1
1–0
0–1
1–0
Rev. 1.1, 2007-02
9
09072006-N4GC-EREN
QIMONDA [ QIMONDA AG ]
