Internet Data Sheet
HY[B/I]39SC128[800/160]FE
128-MBit Synchronous DRAM
2
Pin Configuration
This chapter contains the pin configuration for the ×8, ×16 organization of the SDRAM.
2.1
Pin Configuration
Listed below are the pin configurations sections for the various signals of the SDRAM.
TABLE 3
Pin Configuration of the SDRAM
Ball No. Name Pin
Buffer
Function
Type Type
Clock Signals ×8/×16 Organization
38
37
CLK
CKE
I
I
LVTTL
LVTTL
Clock Signal CK
Clock Enable
Control Signals ×8/×16 Organization
18
17
16
19
RAS
CAS
WE
I
I
I
I
LVTTL
LVTTL
LVTTL
LVTTL
Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE)
CS
Chip Select
Address Signals ×8/×16 Organization
20
21
23
24
25
26
29
30
31
32
33
34
22
35
BA0
BA1
A0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Bank Address Signals 1:0
Address Signal 9:0, Address Signal 10/Auto precharge
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
Rev. 1.1, 2007-02
09072006-N4GC-EREN
5
QIMONDA [ QIMONDA AG ]
