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HYI18T512160B2F-25F 参数 Datasheet PDF下载

HYI18T512160B2F-25F图片预览
型号: HYI18T512160B2F-25F
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 32MX16, 0.4ns, CMOS, PBGA84, GREEN, PLASTIC, TFBGA-84]
分类和应用: 时钟动态存储器双倍数据速率内存集成电路
文件页数/大小: 69 页 / 3834 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HY[B/I]18T512[40/80/16]0B2[C/F](L)  
512-Mbit Double-Data-Rate-Two SDRAM  
TABLE 27  
Single-ended AC Input Test Conditions  
Symbol  
Condition  
Value  
Unit  
Note  
1)  
VREF  
Input reference voltage  
0.5 x VDDQ  
1.0  
V
1)  
VSWING.MAX  
SLEW  
Input signal maximum peak to peak swing  
Input signal minimum Slew Rate  
V
2)3)  
1.0  
V / ns  
1) Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test.  
2) The input signal minimum Slew Rate is to be maintained over the range from VIH(ac).MIN to VREF for rising edges and the range from VREF to  
IL(ac).MAX for falling edges as shown in Figure 4  
V
3) AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative  
transitions.  
FIGURE 4  
Single-ended AC Input Test Conditions Diagram  
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Rev. 1.12, 2007-05  
31  
10062006-YPTZ-CDR7  
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