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HYI18T1G800C2C-3.7 参数 Datasheet PDF下载

HYI18T1G800C2C-3.7图片预览
型号: HYI18T1G800C2C-3.7
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 128MX8, 0.5ns, CMOS, PBGA60, PLASTIC, TFBGA-60]
分类和应用: 时钟动态存储器双倍数据速率内存集成电路
文件页数/大小: 70 页 / 3976 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HY[B/I]18T1G[40/80/16]0C2[C/F](L)  
1-Gbit Double-Data-Rate-Two SDRAM  
5.3  
DC & AC Characteristics  
DDR2 SDRAM pin timing are specified for either single ended  
or differential mode depending on the setting of the EMRS(1)  
“Enable DQS” mode bit; timing advantages of differential  
mode are realized in system design. The method by which the  
DDR2 SDRAM pin timing are measured is mode dependent.  
In single ended mode, timing relationships are measured  
In differential mode, these timing relationships are measured  
relative to the crosspoint of DQS and its complement, DQS.  
This distinction in timing methods is verified by design and  
characterization but not subject to production test. In single  
ended mode, the DQS (and RDQS) signals are internally  
disabled and don’t care.  
relative to the rising or falling edges of DQS crossing at VREF  
.
TABLE 24  
DC & AC Logic Input Levels  
Symbol Parameter  
DDR2-1066  
Min.  
DDR2-667, DDR2-800  
DDR2-533  
Units  
Max.  
Min.  
Max.  
Min.  
Max.  
VIH.DC  
DC input logic  
HIGH  
V
REF + 0.125 VDDQ + 0.3  
V
REF + 0.125 VDDQ + 0.3  
V
REF + 0.125 VDDQ + 0.3  
V
VIL.DC  
VIH.AC  
DC input LOW  
–0.3  
V
REF – 0.125 –0.3  
V
REF – 0.125 –0.3  
V
REF – 0.125 V  
AC input logic  
HIGH  
V
REF + 0.200 –  
V
REF + 0.200 VDDQ + VPEAK  
V
REF + 0.250 VDDQ + VPEAK V  
VIL.AC  
AC input LOW  
V
REF – 0.200 VSSQ VPEAK VREF – 0.200 VSSQ VPEAK VREF – 0.250 V  
TABLE 25  
Single-ended AC Input Test Conditions  
Symbol  
Condition  
Input reference voltage  
Value  
Unit  
Notes  
1)  
VREF  
0.5 × VDDQ  
1.0  
V
1)  
VSWING.MAX  
SLEW  
Input signal maximum peak to peak swing  
Input signal minimum Slew Rate  
V
2)3)  
1.0  
V / ns  
1) Input waveform timing is referenced to the input signal crossing through the VREF level (for DDR2-400 and DDR2-533) and VIH/IL.AC level  
(for DDR2-667, DDR2-800 and DDR2-1066) applied to the device under test.  
2) The input signal minimum Slew Rate is to be maintained over the range from VIH.AC.MIN to VREF for rising edges and the range from VREF to  
V
IL.AC.MAX for falling edges as shown in Figure 4.  
3) AC timings are referenced with input waveforms switching from VIL.AC to VIH.AC on the positive transitions and VIH.AC to VIL.AC on the negative  
transitions.  
Rev. 1.60, 2008-08  
30  
09262007-3YK7-BKKG  
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