欢迎访问ic37.com |
会员登录 免费注册
发布采购

HYI18T1G800C2C-3.7 参数 Datasheet PDF下载

HYI18T1G800C2C-3.7图片预览
型号: HYI18T1G800C2C-3.7
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 128MX8, 0.5ns, CMOS, PBGA60, PLASTIC, TFBGA-60]
分类和应用: 时钟动态存储器双倍数据速率内存集成电路
文件页数/大小: 70 页 / 3976 K
品牌: QIMONDA [ QIMONDA AG ]
 浏览型号HYI18T1G800C2C-3.7的Datasheet PDF文件第12页浏览型号HYI18T1G800C2C-3.7的Datasheet PDF文件第13页浏览型号HYI18T1G800C2C-3.7的Datasheet PDF文件第14页浏览型号HYI18T1G800C2C-3.7的Datasheet PDF文件第15页浏览型号HYI18T1G800C2C-3.7的Datasheet PDF文件第17页浏览型号HYI18T1G800C2C-3.7的Datasheet PDF文件第18页浏览型号HYI18T1G800C2C-3.7的Datasheet PDF文件第19页浏览型号HYI18T1G800C2C-3.7的Datasheet PDF文件第20页  
Internet Data Sheet  
HY[B/I]18T1G[40/80/16]0C2[C/F](L)  
1-Gbit Double-Data-Rate-Two SDRAM  
Ball#  
Name  
Ball  
Type  
Buffer  
Type  
Function  
Other Balls ×16 Organization  
K9  
ODT  
I
SSTL  
On-Die Termination Control  
TABLE 8  
Abbreviations for Ball Type  
Abbreviation  
Description  
I
Standard input-only ball. Digital levels.  
Output. Digital levels.  
I/O is a bidirectional input/output signal.  
Input. Analog levels.  
Power  
O
I/O  
AI  
PWR  
GND  
NC  
Ground  
Not Connected  
TABLE 9  
Abbreviations for Buffer Type  
Abbreviation  
Description  
SSTL  
Serial Stub Terminated Logic (SSTL_18)  
Low Voltage CMOS  
LV-CMOS  
CMOS  
OD  
CMOS Levels  
Open Drain. The corresponding ball has 2 operational states, active low and tristate, and  
allows multiple devices to share as a wire-OR.  
Rev. 1.60, 2008-08  
16  
09262007-3YK7-BKKG  
 复制成功!