Internet Data Sheet
HY[B/I]18T1G[40/80/16]0C2[C/F](L)
1-Gbit Double-Data-Rate-Two SDRAM
FIGURE 1
Chip Configuration for ×4 components, FBGA-60, Top View
ꢃ
ꢆ
ꢅ
ꢉ
ꢂ
ꢈ
ꢁ
ꢊ
ꢇ
$
9''
966
9664
9''4
1)
'46
9664
9664
%
&
'
(
)
*
+
-
1)
'0
'46
1)
9''4
9''4
9''4
9''4
'4ꢃ
'4ꢀ
9664
9664
1)
'4ꢅ
'4ꢆ
966'/
5$6
&$6
$ꢆ
1)
9''/
95()
966
9''
&.
&.
&6
$ꢀ
&.(
%$ꢀ
$ꢃꢀꢄ$3
$ꢅ
:(
%$ꢃ
$ꢃ
2'7
%$ꢆ
9''
966
$ꢂ
$ꢈ
$ꢉ
966
.
/
$ꢁ
$ꢇ
$ꢃꢃ
1&
$ꢊ
9''
$ꢃꢆ
1&
ꢋ$ꢃꢅ
0337ꢀꢁꢂꢀ
Notes
1. VDDL and VSSDL are power and ground for the DLL. VDDL is connected to VDD on the device. VSSDL is connected to VSS
internally. VDD, VDDQ and VSSQ are isolated on the device.
Rev. 1.60, 2008-08
12
09262007-3YK7-BKKG
QIMONDA [ QIMONDA AG ]
