Data Sheet
HY[B/E]18M1G320BF
1-Gbit DDR Mobile-RAM
1.3
Description
The HY[B/E]18M1G320BF is a high-speed CMOS, dynamic random-access memory containing 1,073,741,824 bits. It is
internally configured as a quad-bank DRAM.
The HY[B/E]18M1G320BF uses a double-data-rate architecture to achieve high-speed operation. The double-data-rate
architecture is essentially a 2n pre fetch architecture, with an interface designed to transfer two data words per clock cycle at
the I/O balls. A single READ or WRITE access for the DDR Mobile-RAM consists of a single 2n-bit wide, one clock cycle data
transfer at the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O balls.
The HY[B/E]18M1G320BF is especially designed for mobile applications. It operates from a 1.8V power supply. Power
consumption in self refresh mode is drastically reduced by an On-Chip Temperature Sensor (OCTS); it can further be reduced
by using the programmable Partial Array Self Refresh (PASR).
A conventional data-retaining Power-Down (PD) mode is available as well as a non-data-retaining Deep Power-Down (DPD)
mode. For further power-savings the clock may be stopped during idle periods.
The HY[B/E]18M1G320BF is housed in a 90-ball PG-VFBGA-90-5 package. It is available in Commercial (-0°C to +70°C) and
Extended (-25°C to +85°C) temperature range.
FIGURE 2
Functional Block Diagram
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Rev.1.00, 2007-03
6
02022006-J7N7-GYFP
QIMONDA [ QIMONDA AG ]
