HY[B/E]18L256160B[C/F]X-7.5
256-Mbit Mobile-RAM
Functional Description
Table 10
Timing Parameters for READ
Parameter
Symbol
- 7.5
Units
Notes
min.
–
max.
5.4
6.0
–
Access time from CLK
CL = 3
CL = 2
tAC
tAC
ns
ns
ns
ns
ns
tCK
ns
ns
ns
ns
–
–
–
–
DQ low-impedance time from CLK
DQ high-impedance time from CLK
Data out hold time
tLZ
1.0
3.0
2.5
–
tHZ
7.0
–
tOH
tDQZ
tRC
DQM to DQ High-Z delay (READ Commands)
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
2
–
1)
67
19
45
19
–
1)
1)
1)
tRCD
tRAS
tRP
–
ACTIVE to PRECHARGE command period
PRECHARGE command period
100k
–
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
During READ bursts, the valid data-out element from the starting column address is available following the CAS
latency after the READ command. Each subsequent data-out element is valid nominally at the next positive clock
edge. Upon completion of a READ burst, assuming no other READ command has been initiated, the DQs go to
High-Z state.
Figure 13 and Figure 14 show single READ bursts for each supported CAS latency setting.
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Figure 13 Single READ Burst (CAS Latency = 2)
Data Sheet
18
Rev. 1.11, 2007-01
07142005-CR47-RB2E
QIMONDA [ QIMONDA AG ]
