Internet Data Sheet
HY[B/I]39SC256[80/16]0F[E/F]
256-MBit Synchronous DRAM
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Overview
This chapter lists all main features of the product family HY[B/I]39SC256[80/16]0F[E/F] and the ordering information.
1.1
Features
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Fully Synchronous to Positive Clock Edge
0 to 70 °C Operating Temperature for HYB...
-40 to 85 °C Operating Temperature for HYI...
Four Banks controlled by BA0 & BA1
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Auto Refresh (CBR) and Self Refresh
Power Down and Clock Suspend Mode
8192 refresh cycles / 64 ms (7.8 µs)
Random Column Address every CLK (1-N Rule)
Single 3.3 V ± 0.3 V Power Supply
LVTTL Interface
Programmable CAS Latency: 2 & 3
Programmable Wrap Sequence: Sequential or Interleave
Programmable Burst Length: 1, 2, 4, 8 and full page
Multiple Burst Read with Single Write Operation
Automatic and Controlled Precharge Command
Data Mask for Read / Write control (x8, x16)
Data Mask for Byte Control (x16)
Plastic Packages
– PG-TSOPII-54 (400mil width)
– PG-TFBGA-54 (12 mm x 8 mm)
RoHS compliant product
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TABLE 1
Performance
Product Type Speed Code
–6
–7
Unit
Speed Grade
PC166–333
PC143–333
—
PC133–2221)
Max. Clock Frequency
@CL3
@CL2
fCK3
tCK3
tAC3
tCK2
tAC2
166
6
143
7
MHz
ns
5.4
7.5
5.4
5.4
7.5
5.4
ns
ns
ns
1) Max. Frequency CL/tRCD / tRP
Rev. 1.25, 2007-06
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03062006-NMGU-CQ9D
QIMONDA [ QIMONDA AG ]
