Internet Data Sheet
HYB39SC128[16/32]9EE
128-MBit Synchronous DRAM
2
Chip Configuration
This chapter contains the chip configuration table, the TSOP and TFBGA package drawing for the ×16 und ×32 organization
of the SDRAM.
2.1
Ball Description for TSOP
Listed below are the chip configurations sections for the various signals of the SDRAM for TSOP
TABLE 3
Chip Configuration of the SDRAM in TSOP
Ball No. Name
Pin
Buffer
Function
Type Type
Clock Signals ×16 Organization
38
37
CLK
CKE
I
I
LVTTL
LVTTL
Clock Signal CK
Clock Enable
Clock Signals ×32 Organization
68
67
CLK
CKE
I
I
LVTTL
LVTTL
Clock Signal CK
Clock Enable
Control Signals ×16 Organization
18
17
16
19
RAS
CAS
WE
I
I
I
I
LVTTL
LVTTL
LVTTL
LVTTL
Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable
(WE)
CS
Chip Select
Control Signals ×32 Organization
19
18
17
20
RAS
CAS
WE
I
I
I
I
LVTTL
LVTTL
LVTTL
LVTTL
Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable
(WE)
CS
Chip Select
Rev. 1.00, 2006-10
10302006-7FCJ-R0SX
5
QIMONDA [ QIMONDA AG ]
