Internet Data Sheet
HYB39SC128[16/32]9EE
128-MBit Synchronous DRAM
1.2
Description
The HY[B/E]39SC128[16/32]9E[E/F] are four bank
Synchronous DRAM’s organized as 8 MBit × 16 and
4 MBit × 32 respectively. These synchronous devices
achieve high speed data transfer rates for CAS latencies by
employing a chip architecture that prefetches multiple bits
and then synchronizes the output data to a system clock. The
chip is fabricated with advanced 0.11 µm 128-MBit DRAM
process technology.
output circuits are synchronized with the positive edge of an
externally supplied clock.
Operating the four memory banks in an interleave fashion
allows random access operation to occur at a higher rate than
is possible with standard DRAMs. A sequential and gapless
data rate is possible depending on burst length, CAS latency
and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are
supported. These devices operate with a single 3.3 V ± 0.3 V
power supply. All 128-Mbit components are available in PG–
TSOPII–54, PG–TSOPII–86 packages. See Table 2 for
product features.
The device is designed to comply with all industry standards
set for synchronous DRAM products, both electrically and
mechanically. All of the control, address, data input and
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type
Organization
Clock (MHz)
Package
Note
1)
HYB39SC128169EE–6
HYB39SC128329EE–6
HYB39SC128169EE–7
HYB39SC128329EE–7
HYB39SC128169EE–7.5
HYB39SC128329EE–7.5
× 16
× 32
× 16
× 32
× 16
× 32
166
PG-TSOPII-54
PG-TSOPII-86
PG-TSOPII-54
PG-TSOPII-86
PG-TSOPII-54
PG-TSOPII-86
143
133
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.00, 2006-10
4
10302006-7FCJ-R0SX
QIMONDA [ QIMONDA AG ]
