Internet Data Sheet
HY[I/B]39S512[40/80/16]0A[E/T]
512-Mbit Synchronous DRAM
2
Configuration
This chapter contains the pin configuration table and the TSOP package drawing.
2.1
Pin Configuration
Listed below are the pin configurations sections for the various signals of the SDRAM.
TABLE 3
Ball Configuration of the SDRAM
Ball No. Name Pin
Buffer
Function
Type Type
Clock Signals x4/ x8/ x16 Organization
38
37
CLK
CKE
I
I
LVTTL
LVTTL
Clock Signal CLK
Clock Enable
Control Signals x4/ x8/ x16 Organization
18
17
16
19
RAS
CAS
WE
I
I
I
I
LVTTL
LVTTL
LVTTL
LVTTL
Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE)
CS
Chip Select
Address Signals x4/ x8/ x16 Organization
20
21
23
24
25
26
29
30
31
32
33
34
22
35
36
BA0
BA1
A0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Bank Address Signals 1:0
Address Signal 9:0, Address Signal 10/Auto precharge
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
Rev. 1.52, 2007-06
5
03292006-6Y91-0T2Z
QIMONDA [ QIMONDA AG ]
