Internet Data Sheet
HY[I/B]39S512[40/80/16]0A[E/T]
512-Mbit Synchronous DRAM
1
Overview
This chapter lists all main features of the product family HY[I/B]39S512[40/80/16]0A[E/T] and the ordering information.
1.1
Features
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Fully Synchronous to Positive Clock Edge
0 to 70 °C Operating Temperature for HYB...
-40 to 85 °C Operating Temperature for HYI...
Four Banks controlled by BA0 & BA1
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Data Mask for Byte Control (x16)
Auto Refresh (CBR) and Self Refresh
Power Down and Clock Suspend Mode
8192 refresh cycles / 64 ms (7.8 µs)
Random Column Address every CLK (1-N Rule)
Single 3.3 V ± 0.3 V Power Supply
LVTTL Interface
Programmable CAS Latency: 2 & 3
Programmable Wrap Sequence: Sequential or Interleave
Programmable Burst Length: 1, 2, 4, 8 and full page
Multiple Burst Read with Single Write Operation
Automatic and Controlled Precharge Command
Data Mask for Read / Write control (x4, x8, x16)
Plastic Package : P(G)-TSOPII-54
RoHS compliant product
TABLE 1
Performance
Product Type Speed Code
–7.5
Unit
Speed Grade
PC133–3331)
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Max. Clock Frequency
@CL3
@CL2
fCK3
tCK3
tAC3
tCK2
tAC2
133
7.5
5.4
10
MHz
ns
ns
ns
6
ns
1) Max. Frequency CL/tRCD / tRP
Rev. 1.52, 2007-06
3
03292006-6Y91-0T2Z
QIMONDA [ QIMONDA AG ]
