Internet Data Sheet
HY[I/B]39S512[40/80/16]0A[E/T]
512-Mbit Synchronous DRAM
4.2
AC Characteristics
TABLE 12
AC Timing - Absolute Specifications
Parameter
Symbol
–7.5
Unit Note1)2)3)
PC133–333
Min.
Max.
Clock and Clock Enable
Clock Frequency
tCK
tAC
7.5
10
—
—
ns
ns
CL3
CL2
Access Time from Clock
—
—
5.4
6
ns
ns
CL3
CL2
3)4)5)
Clock High Pulse Width
Clock Low Pulse Width
Transition time
tCH
tCL
tT
2.5
2.5
0.3
—
ns
ns
ns
—
1.2
Setup and Hold Times
Input Setup Time
6)
6)
6)
6)
tIS
1.5
0.8
1.5
0.8
2
—
—
—
—
—
7.5
ns
ns
ns
ns
tCK
ns
Input Hold Time
tIH
CKE Setup Time
tCKS
tCKH
tRSC
tSB
CKE Hold Time
Mode Register Set-up to Active delay
Power Down Mode Entry Time
Common Parameters
Row to Column Delay Time
Row Precharge Time
0
7)
7)
7)
7)
tRCD
tRP
tRAS
tRC
20
20
45
67
67
15
1
—
ns
ns
ns
ns
ns
ns
tCK
—
Row Active Time
100k
—
Row Cycle Time
Row Cycle Time during Auto Refresh
Activate(a) to Activate(b) Command period
CAS(a) to CAS(b) Command period
Refresh Cycle
tRFC
tRRD
tCCD
—
7)
—
—
Refresh Period (8192 cycles)
Self Refresh Exit Time
Data Out Hold Time
tREF
tSREX
tOH
–
1
3
64
—
—
ms
tCK
ns
3)5)
Read Cycle
Data Out to Low Impedance Time
Data Out to High Impedance Time
DQM Data Out Disable Latency
tLZ
1
—
7
ns
ns
tCK
tHZ
3
tDQZ
—
2
Rev. 1.52, 2007-06
15
03292006-6Y91-0T2Z
QIMONDA [ QIMONDA AG ]
