Internet Data Sheet
HY[I/B]39S512[40/80/16]0A[E/T]
512-Mbit Synchronous DRAM
TABLE 8
DC Characteristics
Parameter
Symbol
Values
Unit Note/
Test Condition
Min. Max.
1)
Supply Voltage
VDD
VDDQ
VIH
3.0
3.0
2.0
3.6
3.6
V
V
1)
I/O Supply Voltage
1)2)
1)2)
1)
Input high voltage
VDDQ + 0.3 V
Input low voltage
VIL
–0.3 +0.8
V
Output high voltage (IOUT = – 4.0 mA)
Output low voltage (IOUT = 4.0 mA)
VOH
VOL
2.4
—
—
V
1)
0.4
+5
+5
V
Input leakage current, any input (0 V < VIN < VDD, all other inputs = 0 V) IIL
–5
–5
µA
µA
—
—
Output leakage current (DQs are disabled, 0 V < VOUT < VDDQ
)
IOL
1) All voltages are referenced to VSS
2)
VIH may overshoot to VDDQ + 2.0 V for pulse width of < 4ns with 3.3 V. VIL may undershoot to -2.0 V for pulse width < 4.0 ns with 3.3 V.
Pulse width measured at 50% points with amplitude measured peak to DC reference.
TABLE 9
Input and Output Capacitances
Parameter
Symbol
Values
Unit
Note
Min.
Max.
1)2)
1)2)
Input Capacitances: CK
CI1
CI2
2.5
2.5
3.5
3.8
pF
pF
Input Capacitance
(A0-A12, BA0, BA1, RAS, CAS, WE, CS, CKE, DQM)
1)2)
Input/Output Capacitance (DQ)
CI0
4.0
6.0
pF
1)
VDD,VDDQ = 3.3 V ± 0.3 V, f = 1 MHz, TA see Table 7
2) Capacitance values are shown for TSOP-54 packages. Capacitance values for TFBGA packages are lower by 0.5 pF
Rev. 1.52, 2007-06
13
03292006-6Y91-0T2Z
QIMONDA [ QIMONDA AG ]
