Internet Data Sheet
HYB25DC512[800/160]C[E/F]
512-Mbit Double-Data-Rate SDRAM
%ꢀ$ꢀꢅꢀ %ꢀ$ꢀꢁꢀ $ꢀꢅꢀꢆꢀ $ꢀꢅꢀꢅꢀ $ꢀꢅꢀꢁꢀ
ꢁꢀ
UHꢀ ꢀJꢀꢃꢀDꢀ ꢀGꢀGꢀUꢀ
$ꢀꢉꢀ
$ꢀꢇꢀ
$ꢀꢊꢀ
$ꢀꢂꢀ
$ꢀꢋꢀ
$ꢀꢈꢀ $ꢀꢌꢀ $ꢀꢆꢀ $ꢀꢅꢀ $ꢀꢁꢀ
ꢁꢀ
'ꢀ6ꢀ
'ꢀ/ꢀ/ꢀ
ꢅꢀ
2ꢀSHꢀ ꢀUꢀDWꢀꢀLQꢀ ꢀJꢀꢀ0ꢀ2ꢀ'ꢀ(ꢀ
Zꢀ
Zꢀ
Zꢀ
Zꢀ
0ꢀ3ꢀ%ꢀ7ꢀꢁꢀꢈꢉꢀ ꢀꢁꢀ
TABLE 8
Extended Mode Register
Field
Bits
Type1)
Description
DLL Status
DLL
0
w
0B
1B
Enabled
Disabled
DS
1
Drive Strength
0B
1B
Normal
Weak
MODE
[12:3]
Operating Mode
00000000000BNormal Operation
Notes
1. A2 must be 0 to provide compatibility with early DDR devices
2. All other bit combinations are RESERVED.
1) w = write only register bit
Rev. 1.3, 2006-12
14
03292006-W2FE-ELDX
QIMONDA [ QIMONDA AG ]
