Internet Data Sheet
HYB25DC128[800/160]C[E/F]
128-Mbit Double-Data-Rate SDRAM
3
Functional Description
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TABLE 6
Mode Register Definition
Field
BL
Bits
Type1) Description
Burst Length
[2:0]
W
Number of sequential bits per DQ related to one read/write command.
Note: All other bit combinations are RESERVED.
001B
010B
011B
2
4
8
BT
CL
3
Burst Type
See Table 7 for internal address sequence of low order address bits.
0 Sequential
1 Interleaved
[6:4]
CAS Latency
Number of full clocks from read command to first data valid window.
Note: All other bit combinations are RESERVED.
010B
011B
2
3
110B 2.5
101B 1.5
Note: CL = 1.5 for DDR200 components only
Operating Mode
MODE [11:7]
Note: All other bit combinations are RESERVED.
000000 Normal Operation without DLL Reset
000010 Normal Operation with DLL Reset
1) W = write only register bit
Rev. 1.1, 2007-01
11
03062006-JXUK-E7R1
QIMONDA [ QIMONDA AG ]
