Internet Data Sheet
HYB25DC512[80/16]0B[E/F]
Double-Data-Rate SDRAM
1
Overview
This chapter lists all main features of the product family HYB25DC512[80/16]0B[E/F] and the ordering information.
1.1
Features
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Double data rate architecture: two data transfers per clock cycle
Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
DQS is edge-aligned with data for reads and is center-aligned with data for writes
Differential clock inputs (CK and CK)
Four internal banks for concurrent operation
Data mask (DM) for write data
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
Burst Lengths: 2, 4, or 8
CAS Latency: 1.5 (DDR200 only), 2, 2.5, 3
Auto Precharge option for each burst access
Auto Refresh and Self Refresh Modes
RAS-lockout supported tRAP = tRCD
7.8 µs Maximum Average Periodic Refresh Interval
2.5 V (SSTL_2 compatible) I/O
V
V
DDQ = 2.5 V ± 0.2 V (DDR200, DDR266, DDR333); VDDQ = 2.6 V ± 0.1 V (DDR400B)
DD = 2.5 V ± 0.2 V (DDR200, DDR266, DDR333); VDD = 2.6 V ± 0.1 V (DDR400B)
Standard Temperature Range (0 °C - +70 °C)
PG-TSOPII-66 and PG-TFBGA-60 packages
RoHS1) compliant product types available (green product)
TABLE 1
Performance
Product Type Speed Code
–5
–6
Unit
Speed Grade
Component
@CL3
DDR400B
200
DDR333
166
—
Max. Clock Frequency
fCK3
MHz
MHz
MHz
@CL2.5
@CL2
fCK2.5
fCK2
166
166
133
133
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.2, 2007-04
3
04112007-FHBX-O8HD
QIMONDA [ QIMONDA AG ]
