Internet Data Sheet
HYB25DC512[80/16]0B[E/F]
Double-Data-Rate SDRAM
2.2
Configuration of PG-TFBGA-60
The ball configuration of a DDR SDRAM is listed by function in Table 6. The abbreviations used in the Pin#/Buffer# column are
explained in Table 7 and Table 8 respectively.
TABLE 6
Ball Configuration
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
Clock Signals
G2
CK1
CK1
CKE
I
I
I
SSTL
SSTL
SSTL
Clock Signal
G3
Complementary Clock Signal
Clock Enable
H3
Control Signals
H7
G8
G7
H8
RAS
CAS
WE
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Row Address Strobe
Column Address Strobe
Write Enable
CS
Chip Select
Address Signals
J8
BA0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Bank Address Bus 2:0
Address Bus 12:0
J7
BA1
A0
K7
L8
L7
M8
M2
L3
L2
K3
K2
J3
A1
A2
A3
A4
A5
A6
A7
A8
A9
K8
A10
AP
A11
A12
J2
H2
Rev. 1.2, 2007-04
9
04112007-FHBX-O8HD
QIMONDA [ QIMONDA AG ]
