Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
2
Pin Configuration
The pin configuration of a DDR SDRAM is listed by function in Table 4 (60 pins). The abbreviations used in the Pin#/Buffer#
column are explained in Table 5 and Table 6 respectively. The pin numbering for FBGA is depicted in Figure 1 and that of the
TSOP package in Figure 2
TABLE 4
Pin Configuration of DDR SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
Clock Signals
G2, 45
CK
I
SSTL
Clock Signal
Note: CK and CK are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of
CK and negative edge of CK. Output (read) data is referenced to
the crossings of CK and CK (both directions of crossing).
G3, 46
H3, 44
CK
I
I
SSTL
SSTL
Complementary Clock Signal
CKE
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal
clock signals and device input buffers and output drivers. Taking CKE
Low provides Precharge Power-Down and Self Refresh operation (all
banks idle), or Active Power-Down (row Active in any bank). CKE is
synchronous for power down entry and exit, and for self refresh entry.
CKE is asynchronous for self refresh exit. CKE must be maintained high
throughout read and write accesses. Input buffers, excluding CK, CK and
CKE are disabled during power-down. Input buffers, excluding CKE, are
disabled during self refresh. CKE is an SSTL_2 input, but will detect an
LVCMOS LOW level after VDD is applied on first power up. After VREF has
become stable during the power on and initialization sequence, it must
be mantained for proper operation of the CKE receiver. For proper self-
refresh entry and exit, VREF must be mantained to this input.
Control Signals
H7, 23
RAS
CAS
WE
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Row Address Strobe
Column Address Strobe
Write Enable
G8, 22
G7, 21
H8, 24
CS
Chip Select
Note: All commands are masked when CS is registered HIGH. CS
provides for external bank selection on systems with multiple
banks. CS is considered part of the command code. The standard
pinout includes one CS pin.
Address Signals
J8, 26
J7, 27
BA0
BA1
I
I
SSTL
SSTL
Bank Address Bus 2:0
Note: BA0 and BA1 define to which bank an Active, Read, Write or
Precharge command is being applied. BA0 and BA1 also
determines if the mode register or extended mode register is to be
accessed during a MRS or EMRS cycle.
Rev. 1.70, 2007-11
7
03062006-PFFJ-YJY2
QIMONDA [ QIMONDA AG ]
