Internet Data Sheet
HYB25D512[400/160/800]C[E/T/F/C](L)
512-Mbit Double-Data-Rate SDRAM
%
$
ꢅꢀ
%
$
ꢁꢀ
ꢁꢀ
Uꢀ
$
ꢅ
ꢆꢀ
$
ꢅ
ꢅꢀ
$
ꢅ
ꢁꢀ
UD LQ
Zꢀ
$
ꢉꢀ
$
ꢇꢀ
$
ꢊꢀ
$
ꢂꢀ
$
ꢋꢀ
&/
Zꢀ
$
ꢈꢀ
$
ꢌꢀ
7ꢀ
$ꢆꢀ
$
%
ꢅꢀ
/ꢀ
$ꢁꢀ
ꢀ
%
ꢁꢀ
UH
2S
H
W
Jꢀ0
2'
(ꢀ
JꢃꢀD
G
G
Zꢀ
Zꢀ
0
3
%
7
ꢁ
ꢈꢇꢁꢀ
TABLE 7
Mode Register Definition
Field Bits
Type1) Description
Burst Length
BL
[2:0]
w
Number of sequential bits per DQ related to one read/write command.
Note: All other bit combinations are RESERVED.
001B
010B
011B
2
4
8
BT
CL
3
Burst Type
See Table 8 for internal address sequence of low order address bits.
0B
1B
Sequential
Interleaved
[6:4]
CAS Latency
Number of full clocks from read command to first data valid window.
Note: All other bit combinations are RESERVED.
010B
011B
2
3
110B 2.5
MODE [12:7]
Operating Mode
Note: All other bit combinations are RESERVED.
000000B Normal Operation without DLL Reset
000010B Normal DLL Reset
1) w = write only register bit
Rev. 1.31, 2006-09
15
03292006-3TFJ-HNV3
QIMONDA [ QIMONDA AG ]
