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HYB25D256400BTL-6 参数 Datasheet PDF下载

HYB25D256400BTL-6图片预览
型号: HYB25D256400BTL-6
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 64MX4, 0.7ns, CMOS, PDSO66]
分类和应用: 时钟动态存储器双倍数据速率光电二极管内存集成电路
文件页数/大小: 83 页 / 3071 K
品牌: QIMONDA [ QIMONDA AG ]
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HYB25D256[400/800/160]B[T/C](L)  
256-Mbit Double Data Rate SDRAM  
Functional Description  
3.2.1  
Burst Length  
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The  
burst length determines the maximum number of column locations that can be accessed for a given Read or Write  
command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types.  
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.  
When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All  
accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is  
reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst  
length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column  
address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the  
starting location within the block. The programmed burst length applies to both Read and Write bursts.  
3.2.2  
Burst Type  
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the  
burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the  
burst type and the starting column address, as shown in Table 5.  
Table 5  
Burst Definition  
Burst  
Starting Column Address  
Order of Accesses Within a Burst  
Length  
A2  
A1  
A0  
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Type = Sequential  
Type = Interleaved  
0-1  
2
4
0-1  
1-0  
1-0  
0
0
1
1
0
0
1
1
0
0
1
1
0-1-2-3  
0-1-2-3  
1-2-3-0  
1-0-3-2  
2-3-0-1  
2-3-0-1  
3-0-1-2  
3-2-1-0  
8
0
0
0
0
1
1
1
1
0-1-2-3-4-5-6-7  
1-2-3-4-5-6-7-0  
2-3-4-5-6-7-0-1  
3-4-5-6-7-0-1-2  
4-5-6-7-0-1-2-3  
5-6-7-0-1-2-3-4  
6-7-0-1-2-3-4-5  
7-0-1-2-3-4-5-6  
0-1-2-3-4-5-6-7  
1-0-3-2-5-4-7-6  
2-3-0-1-6-7-4-5  
3-2-1-0-7-6-5-4  
4-5-6-7-0-1-2-3  
5-4-7-6-1-0-3-2  
6-7-4-5-2-3-0-1  
7-6-5-4-3-2-1-0  
Data Sheet  
17  
Rev. 1.21, 2004-07  
02102004-TSR1-4ZWW  
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