HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM
Pin Configuration
CKE
CK
CK
CS
WE
CAS
RAS
Bank3
Bank2
Bank1
CK, CK
DLL
Mode
Registers
13
8192
Bank0
Memory
Array
Data
13
(8192 x 256x 32)
16
16
16
32
Sense Amplifiers
1
DQS
Generator
DQ0-DQ15,
DM
COL0
Mask
DQS
Input
Register
1
I/O Gating
DM Mask Logic
32
2
LDQS, UDQS
1
1
A0-A11,
BA0, BA1
Write
15
1
FIFO
1
&
32
2
32
2
256
Drivers
(x32)
16
16
16
16
16
clk
clk
Column
Decoder
in
out
Data
8
COL0
CK,
CK
Column-Address
Counter/Latch
9
COL0
2
1
Figure 5
Notes:
Block Diagram (16Mb × 16)
1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does
not represent an actual circuit implementation.
2. UDM and LDM are unidirectional signals (input only), but is internally loaded to match the load of the
bidirectional DQ, UDQS and LDQS signals.
Data Sheet
14
Rev. 1.21, 2004-07
02102004-TSR1-4ZWW
QIMONDA [ QIMONDA AG ]
