HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM
Functional Description
Table 8
Current State CKE n-1
Previous Current
Truth Table 2: Clock Enable (CKE)
CKEn
Command n
Action n
Notes
Cycle
Cycle
Self Refresh
Self Refresh
Power Down
Power Down
All Banks Idle
All Banks Idle
L
L
L
X
Maintain Self-Refresh
Exit Self-Refresh
–
1)
H
L
Deselect or NOP
X
L
Maintain Power-Down
Exit Power-Down
–
–
L
H
L
Deselect or NOP
Deselect or NOP
AUTO REFRESH
Deselect or NOP
H
H
Precharge Power-Down Entry –
L
Self Refresh Entry
–
–
–
Bank(s) Active H
H
L
Active Power-Down Entry
–
H
See “Truth Table 3:
Current State Bank n -
Command to Bank n (same
bank)” on Page 49
1) Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (tXSNR) period. A
minimum of 200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
1. CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n.
4. All states and sequences not shown are illegal or reserved.
Table 9
Truth Table 3: Current State Bank n - Command to Bank n (same bank)
Current State CS RAS CAS WE Command
Action
Notes
1) to 6)
Any
Idle
H
L
L
L
L
X
H
L
X
H
H
L
X
H
H
H
L
Deselect
NOP. Continue previous operation
1) to 6)2)
1) to 6)3)
1) to 7)4)
1) to 7)5)
No Operation
Active
NOP. Continue previous operation
Select and activate row
L
AUTO REFRESH
–
–
L
L
MODE
REGISTER SET
1) to 6), 10)
1) to 6), 10)7)
1) to 6), 8)
Row Active
L
L
L
L
H
H
L
L
L
H
L
H
L
Read
Select column and start Read burst
Select column and start Write burst
Deactivate row in bank(s)
Write
L
Precharge
Read
1) to 6), 10)9)
Read
(Auto
H
H
Select column and start new Read
burst
1) to 6), 8)10)
1) to 6), 9)11)
Precharge
Disabled)
L
L
L
H
H
L
L
Precharge
Truncate Read burst, start
Precharge
H
BURST
BURST TERMINATE
TERMINATE
1) to 6), 10), 11)
1) to 6), 10)
Write
(Auto
Precharge
Disabled)
L
L
L
H
H
L
L
L
H
H
L
L
Read
Select column and start Read burst
Select column and start Write burst
Write
1) to 6), 8), 11)
Precharge
Truncate Write burst, start
Precharge
1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table 2: Clock Enable (CKE) and after tXSNR
XSRD has been met (if the previous state was self refresh).
/
t
Data Sheet
49
Rev. 1.21, 2004-07
02102004-TSR1-4ZWW
QIMONDA [ QIMONDA AG ]
