Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
Parameter
Symbol –7
DDR266A
Unit Note1)/ Test
Condition
Min.
Max.
Data hold skew factor
tQHS
—
—
+0.75
+0.75
—
ns
ns
ns
TFBGA
TSOPII
—
Active to Autoprecharge delay
tRAP
tRAS
tRC
tRCD or tRASmin
Active to Precharge command
45
65
20
—
120E+3 ns
—
Active to Active/Auto-refresh command period
Active to Read or Write delay
—
ns
ns
µs
—
tRCD
tREFI
—
—
10)
Average Periodic Refresh Interval
15.6
Auto-refresh to Active/Auto-refresh command period
Precharge command period
Read preamble
tRFC
75
—
ns
ns
tCK
tCK
ns
tCK
ns
tCK
ns
tCK
ns
tCK
—
—
—
—
—
tRP
20
—
tRPRE
tRPST
tRRD
0.9
0.40
15
1.0
0.60
—
Read postamble
Active bank A to Active bank B command
Write preamble
tWPRE
tWPRES
tWPST
tWR
0.25
0
—
—
11)
Write preamble setup time
Write postamble
—
12)
0.40
15
0.60
—
Write recovery time
—
—
—
—
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
tWTR
tXSNR
tXSRD
1
—
75
—
200
—
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT
6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time.
7) HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between VIH(ac) and VIL(ac)
.
t
.
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
10) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
11) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on tDQSS
.
12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
Rev. 1.6, 2007-02
29
03292006-U5AN-6TI1
QIMONDA [ QIMONDA AG ]
