Internet Data Sheet
HYB25D128xxxC[C/E/F/T](L)
128-Mbit Double-Data-Rate SDRAM
TABLE 21
DD Specification
I
–5
–6
–7
Unit
Note1)/ Test Condition
DDR400B
Typ.
DDR333
Typ.
DDR266A
Typ.
Symbol
Max.
Max.
Max.
IDD0
70
90
60
75
50
55
65
70
3
65
65
75
85
4
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
×4/×8 2)3)
75
90
65
75
×16
IDD1
80
100
110
5
70
85
×4/×8
95
80
95
×16
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
4
3.5
25
4.5
30
—
30
36
20
15
9
24
21
13
36
40
70
85
75
90
140
2.8
1.1
170
170
—
20
28
17
24
—
13
18
11
15
—
38
45
32
38
28
30
60
70
65
75
100
1.4
1.1
140
140
×4/×8
43
54
36
45
×16
IDD4R
IDD4W
85
100
120
105
130
190
2.8
—
70
85
×4/×8
100
90
85
100
90
×16
75
×4/×8
100
140
1.4
—
90
110
160
2.8
1.1
215
215
×16
IDD5
IDD6
120
1.4
1.1
180
180
—
Standard version 4)
Low power version 5)
×4/×8
IDD7
210
210
250
250
×16
1) Test conditions for typical values: VDD = 2.5 V ( DDR266, DDR333), VDD = 2.6 V (DDR400), TA = 25 °C, test conditions for maximum
values: VDD = 2.7 V, TA = 10 °C
2)
IDD specifications are tested after the device is properly initialized and measured at 133 MHz for DDR266, 166 MHz for DDR333, and 200
MHz for DDR400.
3) Input slew rate = 1 V/ns.
4) Enables on-chip refresh and address counters.
5) L: Low power version (available on request)
Rev. 1.6, 2007-02
25
03292006-U5AN-6TI1
QIMONDA [ QIMONDA AG ]
