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HYB18M512160BFX 参数 Datasheet PDF下载

HYB18M512160BFX图片预览
型号: HYB18M512160BFX
PDF下载: 下载PDF文件 查看货源
内容描述: DRAM的移动应用程序512兆位的DDR移动-RAM [DRAMs for Mobile Applications 512-Mbit DDR Mobile-RAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 52 页 / 1989 K
品牌: QIMONDA [ QIMONDA AG ]
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HYB18M512160BFX  
512-Mbit DDR Mobile-RAM  
Overview  
1.3  
Description  
The HYB18M512160BFX is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits.  
It is internally configured as a quad-bank DRAM.  
The HYB18M512160BFX uses a double-data-rate architecture to achieve high-speed operation. The double-data-  
rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per  
clock cycle at the I/O pins. A single READ or WRITE access for the DDR Mobile-RAM consists of a single 2n-bit  
wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half clock  
cycle data transfers at the I/O pins.  
The HYB18M512160BFX is especially designed for mobile applications. It operates from a 1.8V power supply.  
Power consumption in self refresh mode is drastically reduced by an On-Chip Temperature Sensor (OCTS); it can  
further be reduced by using the programmable Partial Array Self Refresh (PASR).  
A conventional data-retaining Power-Down (PD) mode is available as well as a non-data-retaining Deep Power-  
Down (DPD) mode. For further power-savings the clock may be stopped during idle periods.  
The HYB18M512160BFX is housed in a 60-ball P-VFBGA package. It is available in Commercial (0°C to 70°C)  
temperature range.  
CKE  
CK  
CK  
CS  
RAS  
CAS  
WE  
Bank 3  
Bank 2  
Bank 1  
Mode  
Registers  
Bank 0  
Memory Array  
13  
13  
8192  
CK/CK  
(8192 x 512 x 32)  
Sense Amplifier  
Data  
16  
16  
16  
A0-A12  
BA0,BA1  
15  
DQ0-  
DQ15  
UDM,  
LDM  
32  
DQS  
Generator  
Input Reg.  
Mask  
IO Gating  
DQM Mask Logic  
2
Write  
FIFO  
&
2
2
UDQS  
LDQS  
4
Drivers  
32  
16  
2
2
clk clk  
out in  
Data  
Column  
Decoder  
CK/CK  
Column Address  
Counter / Latch  
Col0  
9
10  
Col0  
Note 1: The Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent the actual  
circuit implementation  
Note 2: UDM / LDM are unidirectional signals (input only), but internally loaded to match the load of the bidirectional DQ and UDQS / LDQS  
Figure 2  
Functional Block Diagram  
Data Sheet  
8
Rev. 1.10, 2006-11  
04052006-4SYQ-ZRN3