HYB18M512160BFX
512-Mbit DDR Mobile-RAM
Overview
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Overview
1.1
Features
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4 banks × 8 Mbit × 16 organization
Double-data-rate architecture : two data transfers per clock cycle
Bidirectional data strobe (DQS) is transmitted / received with data; to be used in capturing data at the receiver
DQS is edge-aligned with data for READs and center-aligned with data for WRITEs
Differential clock input (CK / CK)
Commands entered on positive CK edge; data and mask data are referenced to both edges of DQS
Four internal banks for concurrent operation
Programmable CAS latency: 2 and 3
Programmable burst length: 2, 4, 8 and 16
Programmable drive strength (full, half, quarter)
Auto refresh and self refresh modes
8192 refresh cycles / 64ms
Auto precharge
Commercial (0°C to +70°C) operating temperature range
TS pad to support Super-Extended temperature range
60-ball Very Thin FBGA package (10.5 × 10.5 × 1.0 mm)
RoHS Compliant Product1)
Power Saving Features
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Low supply voltages: VDD = 1.70 V − 1.90 V, VDDQ = 1.70 V − 1.90 V
Optimized operating (IDD0 , IDD4), self refresh (IDD6) and standby currents (IDD2 , IDD3
DDR I/O scheme with no DLL
Programmable Partial Array Self Refresh (PASR)
Temperature Compensated Self-Refresh (TCSR), controlled by on-chip temperature sensor
Clock Stop, Power-Down and Deep Power-Down modes
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Table 1
Part Number Speed Code
Clock Frequency (fCKmax
Performance
- 7.5
133
66
Unit
MHz
MHz
ns
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CL = 3
CL = 2
Access Time (tACmax
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6.5
Table 2
Item
Memory Addressing Scheme
Addresses
Banks
Rows
BA0, BA1
A0 - A12
A0 - A9
Columns
1)RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and
electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council
of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated
biphenyls and polybrominated biphenyl ethers.
Data Sheet
6
Rev. 1.10, 2006-11
04052006-4SYQ-ZRN3
QIMONDA [ QIMONDA AG ]
