Preliminary Internet Data Sheet
HYS64T128020EML-[3S/3.7/5]-B
Unbuffered DDR2 SDRAM MicroDIMM Modules
Ball No.
Name
Pin
Buffer
Type
Function
Type
200
201
95
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS0
DQS0
DQS1
DQS1
DQS2
DQS2
DQS3
DQS3
DQS4
DQS4
DQS5
DQS5
DQS6
DQS6
DQS7
DQS7
DM0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 39:57
96
101
102
203
204
208
209
7
6
19
18
28
Data Strobes 7:0
Note: The data strobes, associated with one data byte, sourced with data
transfers. In Write mode, the data strobe is sourced by the
controller and is centered in the data window. In Read mode the
data strobe is sourced by the DDR2 SDRAM and is sent at the
leading edge of the data window. DQS signals are complements,
and timing is relative to the crosspoint of respective DQS and DQS.
If the module is to be operated in single ended strobe mode, all
DQS signals must be tied on the system board to VSS and DDR2
SDRAM mode registers programmed appropriately.
27
140
139
71
2. See block diagram for corresponding DQ signals
70
186
185
198
197
99
98
112
120
131
36
177
79
Data Masks 7:0
Note: The data write masks, associated with one data byte. In Write
mode, DM operates as a byte mask by allowing input data to be
written if it is LOW but blocks the write operation if it is HIGH. In
Read mode, DM lines have no effect.
DM1
DM2
DM3
DM4
DM5
DM6
DM7
I
I
I
I
I
I
I
3. ×8 based module
90
206
EEPROM
105
SCL
SDA
I
CMOS
OD
Serial Bus Clock
Note: This signal is used to clock data into and out of the SPD EEPROM.
Serial Bus Data
104
I/O
Note: This is a bidirectional pin used to transfer data into or out of the
SPD EEPROM. A resistor must be connected from SDA to VDDSPD
on the motherboard to act as a pull-up.
Rev. 0.5, 2007-05
8
05212007-7F24-MITO
QIMONDA [ QIMONDA AG ]
