Preliminary Internet Data Sheet
HYS64T128020EML-[3S/3.7/5]-B
Unbuffered DDR2 SDRAM MicroDIMM Modules
Ball No.
Name
BA2
NC
Pin
Buffer
Type
Function
Type
46
I
SSTL
Bank Address Bus 2
Note: Greater than 512Mb DDR2 SDRAMS
Not Connected
NC
–
Note: Less than 1Gb DDR2 SDRAMS
Address Inputs 12:0, Address Input 10/Autoprecharge
161
159
52
158
51
50
157
48
A0
A1
A2
A3
A4
A5
A6
A7
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Note: During a Bank Activate command cycle, defines the row address
when sampled at the crosspoint of the rising edge of CK and falling
edge of CK. During a Read or Write command cycle, defines the
column address when sampled at the cross point of the rising edge
of CK and falling edge of CK. In addition to the column address, AP
is used to invoke autoprecharge operation at the end of the burst
read or write cycle. If AP is HIGH, autoprecharge is selected and
BA[2:0] defines the bank to be precharged. If AP is LOW,
autoprecharge is disabled. During a Precharge command cycle, AP
is used in conjunction with BA[2:0] to control which bank(s) to
precharge. If AP is HIGH, all banks will be precharged regardless
of the state of BA[2:0] inputs. If AP is LOW, then BA[2:0] are used
to define which bank to precharge.
155
154
54
A8
A9
A10
AP
A11
A12
A13
47
153
167
Address Input 13
Note: Modules based on ×4/×8 component
NC
NC
–
Not Connected
Note: Modules based on ×16 component
Data Signals
3
4
9
10
109
110
114
115
12
13
21
22
117
118
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 0:38
Note: Data Input/Output pins
Rev. 0.5, 2007-05
6
05212007-7F24-MITO
QIMONDA [ QIMONDA AG ]
