Internet Data Sheet
HY[B/I]18T256[40/80/16]0B[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
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TABLE 20
EMRS(2) Programming Extended Mode Register Definition (BA[2:0]=010B)
Field Bits
Type1)
Description
BA2
16
w
Bank Address
Note: BA2 is not available on 256 Mbit and 512 Mbit components
0B
BA2 Bank Address
BA
[15:14]
w
Bank Adress
00B BA MRS
01B BA EMRS(1)
10B BA EMRS(2)
11B BA EMRS(3): Reserved
A
[13:8]
7
w
w
Address Bus
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
000000B A Address bits
SRF
Address Bus, High Temperature Self Refresh Rate for TCASE > 85°C
0B
1B
A7 disable
A7 enable 2)
A
[6:4]
3
w
w
Address Bus
000B A Address bits
DCC
Address Bus, Duty Cycle Correction (DCC)
0B
1B
A3 DCC disabled
A3 DCC enabled
Partial Self Refresh for 4 banks
PASR [2:0]
w
Address Bus, Partial Array Self Refresh for 4 Banks3)
Note: Only for 256 Mbit and 512 Mbit components
000B PASR0 Full Array
001B PASR1 Half Array (BA[1:0]=00, 01)
010B PASR2 Quarter Array (BA[1:0]=00)
011B PASR3 Not defined
100B PASR4 3/4 array (BA[1:0]=01, 10, 11)
101B PASR5 Half array (BA[1:0]=10, 11)
110B PASR6 Quarter array (BA[1:0]=11)
111B PASR7 Not defined
Rev. 1.11, 2007-07
24
11172006-LBIU-F1TN
QIMONDA [ QIMONDA AG ]
